multiprocessors MB and shared BRAM
in [FPGA]
|
From: ines_fr on 14 Dec 2009 05:40 hello, I am using spartan 3 starter board (with MB7.1) to work with 2 processors cores using EDK10.1 (my reference is the Xilinx tutorial XAPP996). I want to add, between the two processors, a shared memory BRAM_block_v1_00_a with the controler xps_bram_if_cntlr_v1_00_a. the problem is: when I want to share the bus of the bram controller SPLB, changing the parameter C_SPLB_P2P to 0, nothing happens and the SPLB bus does not connect the two buses mb_plb_0 and mb_plb_1 respectively of the fist CPu and the the second. if someone has an idea please help me because I'm stuck. :( Thanks in advance INES --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.com
From: Goran_Bilski on 15 Dec 2009 02:26 On Dec 14, 11:40 am, "ines_fr" <benhlima_i...(a)yahoo.fr> wrote: > hello, > > I am using spartan 3 starter board (with MB7.1) to work with 2 processors > cores using EDK10.1 (my reference is the Xilinx tutorial XAPP996). I want > to add, between the two processors, a shared memory BRAM_block_v1_00_a with > the controler xps_bram_if_cntlr_v1_00_a. > > the problem is: when I want to share the bus of the bram controller SPLB, > changing the parameter C_SPLB_P2P to 0, nothing happens and the SPLB bus > does not connect the two buses mb_plb_0 and mb_plb_1 respectively of the > fist CPu and the the second. > if someone has an idea please help me because I'm stuck. :( > Thanks in advance > > INES > > --------------------------------------- > This message was sent using the comp.arch.fpga web interface onhttp://www..FPGARelated.com Hi, Not really clear on what you trying to do. One xps_bram_if_cntlr_v1_00_a connects to one PLB. So if the two MB is sharing that PLB bus, don't change anything and just connect the shared PLB bus to the PLB interface on the xps_bram_if_cntlr_v1_00_a. Then just connect the BRAM port on the xps_bram_if_cntlr_v1_00_a to one of the BRAM ports on the BRAM_block_v1_00_a If you don't want the two MB to share the PLB bus, you will need two xps_bram_if_cntlr_v1_00_a where each one is connected to it respectively MB PLB bus. You then connect the BRAM port on the xps_bram_if_cntlr_v1_00_a to the BRAM ports on the BRAM_block_v1_00_a, this will create a shared memory between two seperate PLB busses. Göran Bilski
From: Dave on 15 Dec 2009 14:47 On Dec 14, 5:40 am, "ines_fr" <benhlima_i...(a)yahoo.fr> wrote: > hello, > > I am using spartan 3 starter board (with MB7.1) to work with 2 processors > cores using EDK10.1 (my reference is the Xilinx tutorial XAPP996). I want > to add, between the two processors, a shared memory BRAM_block_v1_00_a with > the controler xps_bram_if_cntlr_v1_00_a. > > the problem is: when I want to share the bus of the bram controller SPLB, > changing the parameter C_SPLB_P2P to 0, nothing happens and the SPLB bus > does not connect the two buses mb_plb_0 and mb_plb_1 respectively of the > fist CPu and the the second. > if someone has an idea please help me because I'm stuck. :( > Thanks in advance > > INES > > --------------------------------------- > This message was sent using the comp.arch.fpga web interface onhttp://www..FPGARelated.com You should be able to add two BRAM controllers (not a BRAM), one connected to each processor's PLB, and add a single BRAM. Connect one of the BRAM's two ports (A or B) to one BRAM controller, and connect the other BRAM port to the other BRAM controller. I'm not sure how the address mapping will work out. I haven't done exactly this, but I have run a BRAM interface to external ports, to interface to a BRAM that is outside of the EDK project (in ISE). Dave
From: ines_fr on 16 Dec 2009 04:41 >On Dec 14, 5:40=A0am, "ines_fr" <benhlima_i...(a)yahoo.fr> wrote: >> hello, >> >> I am using spartan 3 starter board (with MB7.1) to work with 2 processors >> cores using EDK10.1 (my reference is the Xilinx tutorial XAPP996). I want >> to add, between the two processors, a shared memory BRAM_block_v1_00_a wi= >th >> the controler xps_bram_if_cntlr_v1_00_a. >> >> the problem is: when I want to share the bus of the bram controller =A0SP= >LB, >> changing the parameter C_SPLB_P2P to 0, nothing happens and the SPLB bus >> does not connect the two buses mb_plb_0 and mb_plb_1 respectively of the >> fist CPu and the the second. >> if someone has an idea please help me because I'm stuck. :( >> Thanks in advance >> >> INES =A0 =A0 =A0 >> >> --------------------------------------- =A0 =A0 =A0 =A0 >> This message was sent using the comp.arch.fpga web interface onhttp://www= >.FPGARelated.com > >You should be able to add two BRAM controllers (not a BRAM), one >connected to each processor's PLB, and add a single BRAM. Connect one >of the BRAM's two ports (A or B) to one BRAM controller, and connect >the other BRAM port to the other BRAM controller. I'm not sure how the >address mapping will work out. I haven't done exactly this, but I have >run a BRAM interface to external ports, to interface to a BRAM that is >outside of the EDK project (in ISE). > >Dave > Hi, thank you for the idea that helped me a lot! thank you again!!! :)))) INES --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.com
From: ines_fr on 16 Dec 2009 05:49 >>On Dec 14, 5:40=A0am, "ines_fr" <benhlima_i...(a)yahoo.fr> wrote: >>> hello, >>> >>> I am using spartan 3 starter board (with MB7.1) to work with 2 >processors >>> cores using EDK10.1 (my reference is the Xilinx tutorial XAPP996). I >want >>> to add, between the two processors, a shared memory BRAM_block_v1_00_a >wi= >>th >>> the controler xps_bram_if_cntlr_v1_00_a. >>> >>> the problem is: when I want to share the bus of the bram controller >=A0SP= >>LB, >>> changing the parameter C_SPLB_P2P to 0, nothing happens and the SPLB >bus >>> does not connect the two buses mb_plb_0 and mb_plb_1 respectively of >the >>> fist CPu and the the second. >>> if someone has an idea please help me because I'm stuck. :( >>> Thanks in advance >>> >>> INES =A0 =A0 =A0 >>> >>> --------------------------------------- =A0 =A0 =A0 =A0 >>> This message was sent using the comp.arch.fpga web interface >onhttp://www= >>.FPGARelated.com >> >>You should be able to add two BRAM controllers (not a BRAM), one >>connected to each processor's PLB, and add a single BRAM. Connect one >>of the BRAM's two ports (A or B) to one BRAM controller, and connect >>the other BRAM port to the other BRAM controller. I'm not sure how the >>address mapping will work out. I haven't done exactly this, but I have >>run a BRAM interface to external ports, to interface to a BRAM that is >>outside of the EDK project (in ISE). >> >>Dave >> >Hi, >thank you for the idea that helped me a lot! thank you again!!! >:)))) > > >INES > >--------------------------------------- >This message was sent using the comp.arch.fpga web interface on >http://www.FPGARelated.com > Hi, Is that you know how many processors can be integrated on spartan 3 starter boards??? Thanks INES --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.com
|
Pages: 1 Prev: XUPV5-LX110T, DDR2, and EDK (10.1 to be precise) Next: Best clock output pin in Spartan-3 |