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Choice of Language for FPGA programming
On Mon, 07 Sep 2009 12:46:38 +0100, Brian Drummond wrote: I've tried to stay out of this language thread .. how'm I doing? <grin> At least we haven't started a slanging match yet. in the languages I've mentioned, concurrency is well-managed and easy to reason about. As VHDL successfully demonstrate... 8 Sep 2009 04:49
OpenSPARC T1 or T2 on Altera EP2S60 or EP2S90
"Dennis Yurichev" <dennis.yurichev(a)> wrote in message news:6080efe0-0c92-4152-aa85-002586e6a0dd(a) Hi. Does anybody had any real success on running OpenSPARC core on Altera Stratix II? You might get more responses if you change OpenSparc to Leon, I looked at the ... 3 Sep 2009 07:18
usb3.0 PHY wrapper for Xilinx V5/V6 device
On 9ÔÂ1ÈÕ, ÏÂÎç1ʱ25·Ö, "Antti.Luk...(a)" <antti.luk...(a)> wrote: On Sep 1, 6:56 am, "murl...(a)" <water9...(a)> wrote: On 8ÔÂ31ÈÕ, ÏÂÎç3ʱ22·Ö, "Antti.Luk...(a)" <antti.luk...(a)> wrote: On Aug 31, 3:55 am, "murl...@g... 3 Sep 2009 07:19
IMPACT: Verification fails with inidirect SPI programming
Hi, We have one problem regarding Indirect SPI programming using Impact. On our PCB we have Atmel ATDB642D SPI Flash memory (8CN3,CASON) connected to Spartan-3A XC3S1400AFG676. When we try to program the Flash memory using direct sPI programming method everything works just fine. But when we try to program the m... 18 Dec 2008 10:05
dsp boards with multiple AD channels question
Just a question if anybody has some pointers for the following: We need a FPGA board for dsp operations (preferred Xilinx fpga) with 8 channels input with highspeed ADC. Every channel should be sampled at >1 MSPS. There should be enough FPGA and RAM space to buffer results (32 MB for example). Sundance is offerin... 13 Dec 2008 15:18
Adding 128Kx8 SRAM to Spartan 3E FPGA
On a Xilinx Spartan 3e FPGA, I'm attempting to use the XPS MCH EMC memory controller to connect with an 128Kx8 SRAM chip (CY62128DV30LL) using Xilinx 10.1 EDK. If I attempt to specify the address bus as 17 bits in the MHS file I'll get the following error when generating the bitstream: -------------------------... 11 Dec 2008 14:51
Xilinx ISE 10.1 SP3 MPMC NPI VHDL simple sample needed
Hello all, as a newbe with FPGAs I have no clue how to use the NPI interface of the MPMC from Xilinx. I haven't found a really good example. What I need is a simple module in VHDL which reads and writes the memory (maybe a simple memory test). Is there something available ??? Can someone help me out ? Than... 12 Dec 2008 05:57
Looking for FPGA engineer for HD camera project
Hi all, I'm working on a project to create a basic FPGA based digital cinema camera. The FPGA would have to capture a 1920x1080 progressive frames at speeds from 1 to 60 frames/second from a Kodak CCD we've already chosen, convert the stream to a DNG sequence (separate Adobe DNG files, you can find the SDK at... 15 Dec 2008 06:09
Invalid devices when initialising scan chain with Nexys2
G'day all, I am a student studying EE/Physics, and after completing my 2nd year digital design course, I decided to take things further and purchased a digilent Nexys2 for myself to do further tinkering with. I am however struggling with the most basic of tasks: getting digilent's ExPort program to successfully ... 8 Dec 2008 04:47
Back-annotated simulation for Xilinx devices
Hello, I am running a back-annotated timing simulation with Modelsim, on the post-placement&routing VHDL code generated by ISE(Xilinx tool). This VHDL code does not have the initial design signal names or structures, as it comprises only by device-specific components instantiations. This makes debugging very har... 3 Dec 2008 10:24
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