Back-annotated simulation for Xilinx devices
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From: giorgos.puiklis on 3 Dec 2008 07:27 Hello, I am running a back-annotated timing simulation with Modelsim, on the post-placement&routing VHDL code generated by ISE(Xilinx tool). This VHDL code does not have the initial design signal names or structures, as it comprises only by device-specific components instantiations. This makes debugging very hard. Does anyone know how I can find the correspondance between initial signals' names and post-routed signals? Does ISE provide this information? Thank you in advance Giorgos P.
From: Brian Drummond on 3 Dec 2008 09:36 On Wed, 3 Dec 2008 04:27:47 -0800 (PST), giorgos.puiklis(a)gmail.com wrote: >Hello, > >I am running a back-annotated timing simulation with Modelsim, on the >post-placement&routing VHDL code generated by ISE(Xilinx tool). This >VHDL code does not have the initial design signal names or structures, >as it comprises only by device-specific components instantiations. >This makes debugging very hard. > >Does anyone know how I can find the correspondance between initial >signals' names and post-routed signals? Does ISE provide this >information? You can possibly preserve a few specific signal names by adding "keep" attributes. - Brian
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