FPGA

Xilinx ISE, EDK and some ground roules in software development
Hi, I started to learn ISE and EDK 9.1i, but I spent much much time to get things running because they did not work as described in the manuals. Now I write this posting in the hope that someone from Xilinx will read it and consider it for further software development. I tracked down the problems to two sl... 23 Jul 2007 11:54

Uart problem, xapp223 + Spartan3A
I'm using Ken Chapman's uart_tx in a Spartan3A design. The HDL compler can't find the module/primitive, so I wonder if I did everything right here. What I did was the following: - Download and unpack xapp223.zip from Xilinx - Include uart_tx.EDN in my design, no problem - Instantiate it in my code, copy/paste... 15 May 2007 04:53

XILINX ISE 9.1i: DELAYCHAIN by input data
Hi, I am working on an DSP, have problem by data receiving. As listed below, xilinx ise tools build a "DELAYCHAIN" into the circuit, as a result, the data needs 7.956ns from PADS to FlipFlops. My questions are: 1. How can i control the tools, to build or not to build the "DELAYCHAIN". 2. When the data need 7.9... 9 May 2007 07:30

Xilinx VHDL Attribute syntax error
Hello, I was switching UCF lines to VHDL attributes when I came into this syntax error. Can someone suggest what the problem is? #UCF file works fine INST cam2_x0_ibufd_inst DIFF_TERM = TRUE; INST cam1_x0_obufds IOSTANDARD=LVDSEXT_25; -- VHDL attribute DIFF_TERM : boolean; attribute DIFF_TERM of cam2_x0_... 8 May 2007 12:47

Problems in simulation (Webpack 9.1.03i)
Finally I got simulation of logicores in webpack 9.1.03i to work with the ISE simulator. However, these messages appear in the transcript window: Running Fuse ... WARNING:HDLParsers:3583 - File "K:/IP2_J.2/env/Databases/ip/export/rtf/vhdl/src/XilinxCoreLib/div_gen_v1_0.vhd" which file "C:/Xilinx91i/theller/mydesig... 19 Apr 2007 16:04

picoblaze C compiler download wanted
I was hoping to download Francesco Poderico's Picoblaze C compiler today, but unfortunately his domain is expired. Google didn't turn up any other sites from which I can download it; does anyone know of such a location, or would anyone be willing to make it available online or send me a copy? (Provided that doing... 6 May 2007 13:33

ERROR: ::xilinx::Dpm::TOE::execInterrupt doesn't know what to do.
if Xilinx software doesnt know "what todo" how should an regular user know? professional programmers should think not use this kind of error messages in any released software. lets hope xilinx hires a few sometimes in the near future to improve the software quality. ... 11 Apr 2007 05:19

(Xilinx) OPB watchdog timer fails to release RESET
Hi, I'm working on a Microblaze system in a Spartan 3-2000. I am trying to implement a watchdog timer using the opb_timebase_wdt IP core. I'm currently using ISE/EDK 8.2.02i, and the WDT version is 1.00a. The watchdog timer otherwise works fine. I can start/stop/reset the timer with no problem. The trouble is th... 30 Mar 2007 17:19

softcore CPU tools
I've played around with Xilinx PicoBlaze processor, but it's time to step up into 32-bit softcore CPU world for more serious designs, potentially getting in line with embedded OS. I am facing a choice, whether to use always up to date Xilinx EDK tools integrated with ISE and MicroBlaze, which comes with go... 22 Mar 2007 09:09

Comunicate FPGA to Ethernet
Hi people, In last my design, I made a fpga board using IC xc3s400. Now i would like to modify it some following things. I want to add a part into Fpga board. I want to use a chip W5100 to comunicated between FPGA board with ethernet. Do any one can give me some ideas? I hope that someone worked with this ch... 12 Mar 2007 00:21