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XILINX ISE PAR error: CLK0_BUFG_INST is not placed
Dear all, while performing a Place and Route of a reconfigurable project (developed followinf the Early Access User Guide ug208) the par return this error: ERROR: CLock Buffer "Inst_Clockman/CLK0_BUFG_INST" is not placed after constraint resolution. It is a requirement that all clock buffers be "located" during c... 8 Mar 2007 15:05
Routing problem of DCM
Hello, all: When I did the implementation of my design, the map process gave me the following error: --------------------------------------------------------------------------------------------------------- ERROR:PhysDesignRules:1577 - Illegal routing. The DCM_ADV block <....../dcm3_inst/DCM_ADV_INST> has CLK... 9 Mar 2007 15:34
Xilinx platform cable USB API?
Is there a way to access the platform cable USB from a user program (i.e., from outside the Xilinx toolchain) ? What I'd like to do is access a BSCAN module inside my design from a custom win32 application. Many thanks, Guy. ... 28 Feb 2007 06:07
Picobalze in the FPGA
I found a C compiler for picoblaze, it have a manual and some examples. But i try to compile it following the direction in the manual, it was not work. It always noticed "open failes" . i also write a simple C program to test but nothing can make it run. I also try to write a email to author, but he did not answe... 14 Feb 2007 02:41
Virtex 4 SATA redux
I've read some of the heated discussions regarding Virtex 4 and SATA, but I'm still not sure what the answers are. My understanding is that with a modest amount of external circuitry (NOT an external phy) I can build a SATA interface. Some of the Xilinx answer database links regarding SATA are dead. Hopefully someo... 2 Mar 2007 17:43
question about DCM usage in virtex 5
When I use DCM in virtex 5 and do the simulation, the modelsim 6.2e gives the following error message: Failure: (vsim-3808) Incompatible modes for port "clkfx_out". # Time: 0 ps Iteration: 0 Instance: /..../dcm3_inst File: .../ dcm3.vhd Line: 31 # ** Failure: (vsim-3808) Incompatible modes for port "clkin_... 29 Jan 2007 14:44
Timing Diagram Tool
Does anyone know a decent - FREE - timing diagram cad tool? Thanks ... 27 Jan 2007 10:38
Does Xilinx microkernel (xilkernel) support for Condition Variables in Pthread?. That is, can I use code such as: pthread_cond_init pthread_cond_wait Thanks for your help. Pablo AntĂșnez ... 25 Jan 2007 04:52
Hi, when I use ISE8.2 to do synthesis and P&R for my fpga (Virtex 4) design, I got such message: WARNING:XdmHelpers:662 - Period specification "TS_u_DigRF_top_u_v4_clkgen_clk26_buf" references the TNM group "u_DigRF_top_u_v4_clkgen_clk26_buf", which contains both pads and synchronous elements. The... 23 Jan 2007 04:37
Xilinx ISE 8.2
I'm looking for POSITIVE feedback on Xilinx ISE. Yes i realize it has it problems, but It's free. So, I've been looking round the WWW to find some tips on what type of system (Windows, Linux, Intel x86 or EM86_64, AMD, etc) that might result in better software preformace. Also, considering the effects of the Java... 14 Feb 2007 17:02
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