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From: cathy on 29 Jan 2007 10:11
When I use DCM in virtex 5 and do the simulation, the modelsim 6.2e
gives the following error message:
Failure: (vsim-3808) Incompatible modes for port "clkfx_out".
# Time: 0 ps Iteration: 0 Instance: /..../dcm3_inst File: .../
dcm3.vhd Line: 31
# ** Failure: (vsim-3808) Incompatible modes for port
"clkin_ibufg_out".
# Time: 0 ps Iteration: 0 Instance: ....dcm3_inst File: .../dcm3.vhd
Line: 32
# ** Failure: (vsim-3808) Incompatible modes for port "clk0_out".
# Time: 0 ps Iteration: 0 Instance: ..../dcm3_inst File: ..../
dcm3.vhd Line: 33
# ** Failure: (vsim-3808) Incompatible modes for port "locked_out".
# Time: 0 ps Iteration: 0 Instance: ...../dcm3_inst File: ...../
dcm3.vhd Line: 34

I don't know why it told me "incompatible modes for port "clkfx_out".
They are all std_logic type and connected with the std_logic signals.


Tank you very much for your help,
Cathy



I generated the dcm file from the core generator 8.2.03i directly and
here is the .vhd code:
-----------------------------------------------------------------------
---------
-- Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
-----------------------------------------------------------------------
---------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 8.2.03i
-- \ \ Application : xaw2vhdl
-- / / Filename : dcm3.vhd
-- /___/ /\ Timestamp : 01/28/2007 16:17:47
-- \ \ / \
-- \___\/\___\
--
--Command: xaw2vhdl-st F:\core\core8.2\CoreGen\dcm3.xaw F:\core
\core8.2\CoreGen\dcm3
--Design Name: dcm3
--Device: xc5vlx50-1ff676
--
-- Module dcm3
-- Generated by Xilinx Architecture Wizard
-- Written for synthesis tool: XST

library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;

entity dcm3 is
port ( CLKIN_IN : in std_logic;
RST_IN : in std_logic;
CLKFX_OUT : out std_logic;
CLKIN_IBUFG_OUT : out std_logic;
CLK0_OUT : out std_logic;
LOCKED_OUT : out std_logic);
end dcm3;

architecture BEHAVIORAL of dcm3 is
signal CLKFB_IN : std_logic;
signal CLKFX_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal CLK0_BUF : std_logic;
signal GND1 : std_logic_vector (6 downto 0);
signal GND2 : std_logic_vector (15 downto 0);
signal GND3 : std_logic;
component BUFG
port ( I : in std_logic;
O : out std_logic);
end component;

component IBUFG
port ( I : in std_logic;
O : out std_logic);
end component;

-- Period Jitter (unit interval) for block DCM_ADV_INST = 6.67 UI
-- Period Jitter (Peak-to-Peak) for block DCM_ADV_INST = 0.38 ns
-- Period Jitter (unit interval) for block DCM_ADV_INST = 0.03 UI
-- Period Jitter (Peak-to-Peak) for block DCM_ADV_INST = 0.20 ns
component DCM_ADV
generic( CLK_FEEDBACK : string := "1X";
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := FALSE;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
DCM_AUTOCALIBRATION : boolean := TRUE;
DCM_PERFORMANCE_MODE : string := "MAX_SPEED";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DUTY_CYCLE_CORRECTION : boolean := TRUE;
FACTORY_JF : bit_vector := x"F0F0";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := FALSE);
port ( CLKIN : in std_logic;
CLKFB : in std_logic;
DADDR : in std_logic_vector (6 downto 0);
DI : in std_logic_vector (15 downto 0);
DWE : in std_logic;
DEN : in std_logic;
DCLK : in std_logic;
RST : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
PSCLK : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLKDV : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
DRDY : out std_logic;
DO : out std_logic_vector (15 downto 0);
LOCKED : out std_logic;
PSDONE : out std_logic);
end component;

begin
GND1(6 downto 0) <= "0000000";
GND2(15 downto 0) <= "0000000000000000";
GND3 <= '0';
CLKIN_IBUFG_OUT <= CLKIN_IBUFG;
CLK0_OUT <= CLKFB_IN;
CLKFX_BUFG_INST : BUFG
port map (I=>CLKFX_BUF,
O=>CLKFX_OUT);

CLKIN_IBUFG_INST : IBUFG
port map (I=>CLKIN_IN,
O=>CLKIN_IBUFG);

CLK0_BUFG_INST : BUFG
port map (I=>CLK0_BUF,
O=>CLKFB_IN);

DCM_ADV_INST : DCM_ADV
generic map( CLK_FEEDBACK => "1X",
CLKDV_DIVIDE => 2.0,
CLKFX_DIVIDE => 1,
CLKFX_MULTIPLY => 3,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 20.0,
CLKOUT_PHASE_SHIFT => "NONE",
DCM_AUTOCALIBRATION => TRUE,
DCM_PERFORMANCE_MODE => "MAX_SPEED",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "HIGH",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => TRUE,
FACTORY_JF => x"F0F0",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map (CLKFB=>CLKFB_IN,
CLKIN=>CLKIN_IBUFG,
DADDR(6 downto 0)=>GND1(6 downto 0),
DCLK=>GND3,
DEN=>GND3,
DI(15 downto 0)=>GND2(15 downto 0),
DWE=>GND3,
PSCLK=>GND3,
PSEN=>GND3,
PSINCDEC=>GND3,
RST=>RST_IN,
CLKDV=>open,
CLKFX=>CLKFX_BUF,
CLKFX180=>open,
CLK0=>CLK0_BUF,
CLK2X=>open,
CLK2X180=>open,
CLK90=>open,
CLK180=>open,
CLK270=>open,
DO=>open,
DRDY=>open,
LOCKED=>LOCKED_OUT,
PSDONE=>open);

end BEHAVIORAL;

From: Mike Treseler on 29 Jan 2007 12:29
cathy wrote:
> When I use DCM in virtex 5 and do the simulation, the modelsim 6.2e
> gives the following error message:
> Failure: (vsim-3808) Incompatible modes for port "clkfx_out".

> I don't know why it told me "incompatible modes for port "clkfx_out".
> They are all std_logic type and connected with the std_logic signals.

Port mode means direction, not type.
Maybe you have shorted two out ports together.

-- Mike Treseler
From: cathy on 29 Jan 2007 13:17
Thank you, I had a stupid mistake of forgetting to put the in/out
direction in the complonent declaration. Thank you.


From: Mike Treseler on 29 Jan 2007 14:14
cathy wrote:
> Thank you, I had a stupid mistake of forgetting to put the in/out
> direction in the complonent declaration. Thank you.

You are welcome.

This is one reason that I use direct instances
instead of components.


-- Mike Treseler


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