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From: lucaroccasalva on 8 Mar 2007 14:45
Dear all,
while performing a Place and Route of a reconfigurable project
(developed followinf the Early Access User Guide ug208) the par return
this error:
ERROR: CLock Buffer "Inst_Clockman/CLK0_BUFG_INST" is not placed after
constraint resolution. It is a requirement that all clock buffers be
"located" during constraint resolution. PLease coorect this before
continuing".

In the UCF file I placed the following constraint:
INST "Inst_Clockman" AREA_GROUP = "DCM"
INST "Inst_Clockman/DCM_INST" LOC = "DCM_X0Y1";
INST "Inst_Clockman/CLK0_BUFG_INST" LOC = "BUFGMUX7";
AREA_GROUP "DCM" MODE = RECONFIG;
AREA_GROUP "DCM" GROUP = CLOSED;

I also tried removing the INST "Inst_Clockman/CLK0_BUFG_INST" LOC =
"BUFGMUX7"; but the error remain the same.

The software I am using is ISE 8.2iSP1 with PR07 and the device is a
Xilinx Spartan3 xc3s400.

What could I do?

Thank you very much

Luca

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