FPGA

Synchronizing four phase-offset clock domains
I'm working on modifying a design in order to meet my needs and am having trouble coming up with a workable soltuion. It mainly centers around some different clock domains. This design is for a Virtex-4 SX55 FPGA. The base design that I am starting from has 4 ADC inputs which come in with individual source syn... 16 Jan 2007 13:23

LWIP EXAMPLE??
Has anybody any LWIP example?. I try to connect PC and Board. I try to send some package with tcp_write but I have errors because I can't get it. I don't want to implement a webserver, I only want a little code to transmit ethernet data. Thanks ... 12 Jan 2007 04:05

SPI slave problem
Hello Folks, I'm writting a slave SPI code for my FPGA and very sure that my master is generating the right SPI but somehow slave is unable to decode it. I've never used the verilog before so it might be possible that something is wrong with my code. Please advice. _______________________________________... 3 Jan 2007 02:54

ANN: PicoBlaze C: compile to bitstream!
PicoBlaze C compiler has been available for some time already, but until yesterday I never tried it. But today when I type: start build.bat then the following C file ----- cut ----- // This is first PCCOMP Program tested on MicroFpga! // Target was S3-200 with KCPSM3_256S MF-Core #include "..\inc\padma... 23 Dec 2006 08:48

Picoblaze C compiler 1.8.4
Hi all, for the picoblaze funs... you can download the latest version of picoblaze C compiler on my website www.poderico.co.uk the latest version is 1.8.4 In this version you have the optimizer (just started) I've got an example how to use the LCD IF on the Spartan3E starter kit... if you want to have a try.. ... 5 Dec 2006 04:54

problems with verilog SDRAM models
I am trying to write an SDRAM controller in VHDL for a mobile SDR SDRAM that I want to be able to control via an FPGA on the same PCB. I am having trouble with the verilog model. I have used both a samsung and a micron model for the part (two compatible parts). Unfortunately these models are not available in VHDL, ... 4 Dec 2006 13:44

Spartan 3E-Kit
I found the thread about this kit but cannot write there, since it is more than 60 days old. I am seeking for an empty or small project to start with the xilinx ide. Of course I found the sample projects, but a) they are too complex IMO (i do not need the pico blaze yet ) and b) I am having difficulties in creat... 24 Nov 2006 23:49

V5 LXT PCIe Block simulation
I am trying to simulate PCI Express Endpoint Block 1.1 generated by coregen in ModelSim SE. I get the following errors Error: ../../src/pcie_top.v(2153): Module 'PCIE_EP' is not defined Error: ../../test_bench/pcie_ne.v(1221): Module 'PCIE_INTERNAL_1_1' is not defined I have Installed the following as per An... 21 Nov 2006 16:26

Simple questions on IDELAYCTRL
I can't seem to find a document that calls out the XY locations for the IDELAYCTRL. Where is this information found? When I don't use the LOC, the report for P&R says it has used 100% of the IDELAYCTRLs. No surprize. When I look at the FPGA editor I would expext to see all of them listed but instead I only see... 22 Nov 2006 12:16

spartan-3e starter kit and ethernet
Hello, I recently purchased a spartan-3e starter kit from Xilinx. (I have so far been unimpressed with the reference designs supplied with the kit, but that's another subject...) I am trying to use the ethernet connector on the board to communicate with a PC, and so far I have been unsuccessful. I do not want ... 19 Nov 2006 11:07