FPGA

3.3v<->5V
Hi all, I am new to logic design in general, but I am getting an FPGA development board (the Spartan-3 board from xilinx) and I hope to make a small circuit for connecting to an old microcomputer and some SRAM. For this project, I will need a bunch of (~60) 5V I/O lines, but the FPGA's lines are all 3.3V logic. ... 16 Oct 2005 07:26

VHDL : Use concatenation on port mapping
Can someone use logic operations or concatenation within port mapping statments on Xilinx ISE? for example: PacketRAM: packet_dpram PORT map ( data => CAV & DAV & KDATA, wren => CAV or DAV, wraddress => packet_wraddress, rdaddress => packet_rdaddress, wrclock => LHC_CLK, rdclock => INT_CLK, q => packet... 17 Oct 2005 10:25

DDR constraints in Xilinx/UCF, Synplicity?
HELP! How to constrain source-synchronous DDR inputs in Xilinx? In Synplify Pro? Double Data Rate input scenario: CLK = 500MHz (Period = 2ns, Pd/2=1ns, Pd/4=0.5ns) Data rate = 1.0 Gb/sec (Ideal bit valid window = 1ns) time t=0.0 1.0 2.0 3.0 4.0 etc... ___... 12 Oct 2005 08:41

Small C Compiler for Picoblaze
Dear all, last year I started to design the back end of a "Small C" compiler for the picoblaze microcontroller. (You can download it on www.poderico.co.uk) I haven't done much for the last two months... but now I'm ready to continue my development. I'm looking for some help in the development. Do you want to help... 29 Sep 2005 09:33

Sythesis software for Virtex-4
Hi, I are looking to purchase some FPGA software in the very near term for a project utilizing Xilinix's Virtex-4 device. I are relatively new to FPGA design and would appreciate any comments from those who have experience with Virtex-4 regarding FPGA synthesis software options. I have looked at Mentor, Sy... 28 Sep 2005 20:10

chipscope pro
I have a working design where I can see the ouput on the leds .I am using a ML310 board . The design doesnt seem to work when I try to load it through chipscope pro. When I use a ILA core into my design and try to load the design on to the system it always says that "Waiting for Core to be armed, slow or stopped ... 28 Sep 2005 23:16

Xilinx Spartan-3
Hello! I have an application with a Spartan-3 mainboard and 3 spartan-3-based daughterboards -- we had planned on connecting the daughterboards to the mainboard via SATA connectors, and running a 300 Mbps LVDS link in each direction (M->D and D->M). We had hoped that the daughterboards could do clock-recovery of th... 26 Sep 2005 09:24

JTAG USB Circuit
anyboydy knows how to find the circuit or schematic fo make an JTAG USB cable? ... 21 Sep 2005 21:52

Xilinx V2Pro & SATA hard disk
Hi all, Does anyone has implemented a SATA link on Xilinx V2Pro to connect to a hard disk drive ? Indeed, we have the Xilinx XUP V2Pro Dev board from Digilent and it has a SATA connector. So I'm wondering if one can control a hard disk drive from this SATA connector. Furthermore, I would like to mount the disk o... 15 Sep 2005 12:52

ARM IP Core implementation in FPGA
Hi All, i request some of you guys who worked or having knowledge on imlementation of ARM core with MBA bus in FPGA.Basically we are designing two FPGAs in single card with the functionality given below. we are are trying to implement ARM926 IP core and USB2.0 IP CORE in one of the Virtex4 FPGA. Due some con... 14 Sep 2005 07:53