FPGA

floating point alignment issues with xilkernel
Hi! I'm encountering a nasty bug when using the xilkernel with floating point. I have an application that uses the FPU (connected via APU) to the PPC440 (EDK 10.1 SP2). When I run the application standalone everything works fine. However, when I use xilkernel and use my application as starting thread execution s... 25 Jul 2008 08:22

ANNC: Verilog Coding for FPGA Webcast
Lattice is holding a webcast tomorrow, Wednesday, April 9, "Optimizing Verilog Coding for More Efficient FPGA Synthesis." The presenter will be Troy Scott, from our software marketing group. If you're interested, the event takes place live at 11am Pacific, 18:00 GMT. In addition, you will be able to view this web... 8 Apr 2008 19:42

Sparkfun Spartean3e Board
Hi I have a SparkFun Spartan3e development board which uses an ATMEL AT45DB161D serial SPI flash for configuration. Here is a photo: http://www.sparkfun.com/commerce/images/Spartan3EEvalBoard-01-L.jpg I can program the FPGA using JTAG but can not figure out how to get ISE to program the SPI flash. All my att... 20 Jan 2008 17:35

DCR_INTC usage in EDK - where is SR18804?
I'm trying to get the DCR interrupt controller working in EDK 9.1 with xil_kernel on a V4FX12. Hardware builds fine, but I'm not sure how to configure the software platform settings and so forth. In the PDF datasheet for dcr_intc, they make the following statement: "to use this core with EDK design tools, see s... 15 Jan 2008 00:09

DDR SDRAM demo for Spartan-3E starter kit?
I have a Xilinx/Digilent Spartan-3E starter kit Rev D (with 46V32M16 -6T F). Is there any *simple* demo that stores a picture bitmap in the builtin DDR SDRAM and sends the bitmap to the VGA port continously ..? Is it correct that the DDR SDRAM won't go below 75 MHz due the DLL used ..? (Micron indicate that SDR... 8 Jan 2008 12:48

can't install Centos 5.1 x86_64 and Xilinx ISE 9.2 evaluation
I recently upgraded from a Centos 4.5 x86_64 (Red Hat Enterprise 4 Update 5) installation to Centos 5.1. I reinstalled the O/S from scratch. When I try to install Xilinx ISE 9.2 Foundation (Evaluation) on my Centos 5.1 x86_64 machine, the './setup' script in the DVD's root-directory doesn't work. When I ru... 9 Dec 2007 23:56

Asynchronous FIFO and almost empty - bug?
Hi, we are using an asynchronous FIFO to bridge two clock domains. Both domains have "the same" clock speed but different clock oscillators. We shift data phits in the FIFO which always form a data packet. In between a packet data is shifted in continously without a break. Breaks (no shift in) are only allowed... 9 Dec 2007 23:55

Linux capable free/GPL SOFT CPU for XC3S500E?
You can try http://www.niktech.com/ and their Manik CPU It seems to be small enough to fit into the XCS500E with several peripherals. Here is startup description for Spartan-3 Starter Kit http://www.niktech.com/GettingStarted.pdf Vit ... 10 Nov 2007 08:21

Xilinx PCI-Express Endpoint Block IP
There is only 8 bit interface wrapper(pcie_gt_wrapper.v) from Xilinx PCI-Express Endpoint Block IP. it means that it needs 250MHz clk.In general,it is impossible to achieve 250Mhz clk with large design.So,we need 16bit interface wrapper so that the clk can be reduced 125Mhz. it is very easy to implement.is there ... 10 Nov 2007 08:21

ERROR:Simulator:222 - Generated C++ compilation was unsuccessful
Hi, I want to make a simulation. However, I get an error like below. I dont know how to solve this problem. does anybody have an idea about this problem? THE ERROR: Running Fuse ... Compiling vhdl file "C:/work/prj/main.vhd" in Library work. Entity <main> compiled. Entity <main> (Architecture <behavio... 10 Nov 2007 08:21