FPGA

modelsim simulation problem
I am trying to load a EDK design in modelsim for simulation.I can successfully compile the files but when I try to simulate the project, I get the following error. # Loading /home/simulation_library/simtemp/unisim.ppc405(ppc405_v) # ** Warning: (vsim-3479) Time unit 'ps' is less than the simulator resolution (1n... 12 Sep 2005 16:44

Signed addition
Hi I'am a newbe, and know how to add unsigned numbers in Verilog HDL, but how to define a signed number? I've the following situation: reg [7..0] p1 //(is an unsigned value from AD converter) 0..255 reg [7..0] p2 // is the unsigned value that we should have 0..255 now I want to substract p1-p2, to have the di... 11 Sep 2005 10:55

Defining Environment variables inside EDK
Hi, I need to define some environment variable to change the behavior of the synthesis tool in order for my design to compile (XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING). I'd like to define that inside the EDK project, without having to modify my system or user wide environment. I've tried adding that to the system_... 7 Sep 2005 10:19

gal16v8 CUPL problems
Hi After searching more than 3 hours the web, awincupl.exe was found to compile some CUPL code. Personally I find it to bugy, so if there is any better suite to get a ..jed file I would appreciate the information. The programm for a g16v8 needs to have 1 input to decode 8 outputs, unfortunatelly the code atta... 2 Sep 2005 17:04

Hi-Z input
Hallo, have connected an external signal to my spartan 3. When the external peripheral goes into power down mode, the signal goes into Hi-Z state. I have made a process sensitive to the external signal. if (ext_signal = 'Z') then ... Using this syntax the fpga doesn't "see" the high impdance state and ... 1 Sep 2005 10:46

LCD Interface
Hi, I've been struggeling with a long standing problem driving a 320x240 graphic LCD display. I've been using a LCD module with an Epson SED1335 controller chip. In my application the controller is quite susceptible to noise - it resets for no reason, exibits distortion of the image. Googling has come up ... 2 Sep 2005 14:48

CPLD Jitter
The dividers and the phase detector of my experimental frequency synthesizer are implemented in a 15ns Altera MAX7000S CPLD. I've tried different multiplication factors (kN) to see how the close-in phase noise varies. At a 1 KHz offset, I get: -82 dBc/Hz for N=198 (VCO=19.8 MHz, comparison freq = 100 KHz) -95 ... 30 Aug 2005 16:44

Altera NIOS in a Cyclone
Hi: I'm trying to get a NIOS running in an Altera Cyclone FPGA. I'm configuring using a epcs (serial eeprom) then booting from FLASH. THe boot process copies a code image from FPASH to SDRAM then jumps to the start in SDRAM. Running under JTAG is not a problem. Initially I had RESET* going high before Con... 26 Aug 2005 14:35

Writing to Spartan 3 SRAM
Hello all, i am very new to FPGA design and struggling to understand how to write data to Spartan 3 SRAM. I am using verilog and my code looks like something bleow, ------------------------------------------------------------------- cs = 1'b0; ub = 1'b0; lb = 1'b0; we = 1'b0; oe = 1'b1; mem = i // i is ... 26 Aug 2005 15:06

Library of eBooks on FPGA's and other programming stuff
Hi everybody, As I received some emails about the systemC books I had I decided to post this: I'm a student so my interests still change rather fastly :D Since books are really expensive and since I just want to get a "feel" of the topics I'm looking at, I picked the habit of getting myself a lot of ebook... 26 Aug 2005 21:48