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BPSK modulation on Xilinx FPGA
Hi everybody, I'm trying to implement a BPSK modulation. A sin waveform has to be generated at a given frequency (1MHz) with phase offset (binary PSK i.e. 180°) when transition occures on a data wire. Is there any "simple" LogiCORE with BPSK functionality available for my Xilinx Spartan-3 - Board ? My atte... 2 Feb 2006 17:42
Xilinx Legal
All: From our legal group- "Xilinx invests a significant amount in research and development, and vigorously protects and enforces its intellectual property rights resulting from its research and development efforts. It is also correct that when Xilinx licenses its software and tools, Xilinx prohibits its cu... 1 Feb 2006 10:53
porting linux on ml403
Hi All, Iam new to xilinx platfrom. I was trying to port open source linux on Ml403 board. i tried to follow the instructions in the below link. i was getting errors when i was running bZimage. the .elf file was not getting created. Is there an alternative way of acheiv... 8 Feb 2006 19:24
FPGA Journal Article
I'm writing a feature article for FPGA Journal ( about FPGAs and the re-birth of the electronics hobbyist. My theory is that electronics as a hobby went through a "dark age" period, maybe from the early/mid 1970s until recently becuase of the inaccessibility and cost of designing with state-of-... 25 Jan 2006 21:36
Xilinx Spartan3E Sample Pack 3rd party programing support now available
as more and more customers are getting their Sample Packs so I decided to pre release the standalone programming utility for the board, available for immediate download,com_remository/Itemid,53/func,fileinfo/id,8/ this has fully working base functionality for FPGA config and... 11 Jan 2006 13:30
Help! FIR Filter - MATLAB fdatool - VHDL
Hi, I designed a 7th order FIR filter using MATLAB fdatool and obtained the VHDL code using the HDL Coder. I think that in the following part of the code there is a problem (Delay pipe line is an 8 element array, whose elements are 16 bit vectors. filter_in is a 16 bit vector): IF reset = '1' THEN delay_pipeline(... 9 Jan 2006 08:35
ModelSim vsim-3601 message
Good day, I am trying to simulate a design for an Spartan3-200, on Webpack 7.1i SP4 with ModelSim XE III/Starter 6.0a. The design simulates perfectly for a functional simulation, running own .do file on ModelSim. However, if I run the same .do file on the simulation model generated with the "Generate Pos... 5 Jan 2006 07:07
PLX 9056 application
Hello, I am trying to use PLX9056 as an interface between PCI bus and local bus, in manner as simple as possible. I would fill some SRAM on the local bus with certain amount of data (256 or 8K or 32K or 64K words) from uP or FPGA and then tell PLX to take that data and transfer it to PCI bus. The transfer may al... 7 Dec 2005 15:04
Slow FIFO using external SRAM
I need to implement slow FIFO (16-bit wide, max. 10 MHz) using external single-port SRAM connected to the FPGA (Spartan II/III). Does anyone have similar FIFO controller (sync/async) implemented using VHDL? Thanks, Damir ... 2 Dec 2005 08:49
Memory in VHDL
I would like to code the on-chip memory in vendor neutral VHDL. I got it running for a dual-port memory with single clock and same port sizes for the read and write port. However, I need a memory with a 32-bit write port and an 8-bit read port. So far I was not able to code it in VHDL in a way that the Synthesiz... 29 Nov 2005 06:04
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