FPGA

Camera link specification
Hi All, I have a project to get the image data by camera and want to convert them as grayscale information. The camera has Camera Link output. It can be connected directly to universal frame grabber. I am trying to replace the frame grabber by FPGA. Does somebody know or has information how to get camera link s... 25 Oct 2006 09:13

Block Memory Generator: Wrong data in BRAM after initialization with *.ceo File
Ben schrieb: Hi, i'm using Block Memory Generator 2.1 for a 16bit * 1024 RAM implemented in virtex4 BRAM and want to initialize the data with a *.coe file. But if i dump the data from the *.bit file with "data2mem -d" it doesn't match completely with the data from the *.ceo file. for example: * .ceo fi... 17 Oct 2006 11:26

DIFF_TERM and unused pin
Tim Verstraete schrieb: Hey, I have 2 LVDS clock signals and both are terminated with the DIFF_TERM attribute on the LVDS25 input buffer IBUFGDS but i only use 1 of them ... now i want both buffers to stay in my design and not optimized away. Is there a constraint that i can place on that buffer? i ... 15 Oct 2006 06:56

Am I blind or? (Virtex-4 issues)
Hi, Virtex-4 has many new things, one of them is access to CCLK as output after configuration. CCLK control is required to readback data from XCF devices, this approuch is described in Xilinx Application note XAPP482. Until today I did live in believe that this was the reason why startup primitive was modified i... 12 Oct 2006 11:50

Xilinx MicroBlaze 4.00.a source codes released by Xilinx !?
get from Xilinx website http://www.xilinx.com/bvdocs/appnotes/xapp730.zip unzip, then look in /pcores/microblaze_4_00_a/hdl/vhdl that looks like true unscrambled RTL source of the MicroBlaze !? Or am I seeing wrong ? Antti ... 12 Oct 2006 14:29

Open protocol USB JTAG cable
Hi everybody, I'm going to build a USB JTAG cable and I don't know what protocol should I use for communication. The only cable I can fully implement this time is the Digilent USB cable... (according to the code of Zoltan Csizmadia's cable server project) I was trying to reverse engineer Xilinx's USB Platform ca... 6 Oct 2006 21:51

EBR Based FIFO ...
Hi All, The EC/ECP EBR (or Block RAM) can be configured in the following modes (as supported in the hardware): - Single Port RAM (RAM_DQ) - Dual Port RAM (RAM_DP) - True Dual Port RAM (RAM_DP_TRUE) - Read Only Memory (ROM) The EBR block does not have a native hardware support for the FIFO. The way FIFO is c... 27 Sep 2006 21:37

ddr2 sodimm controller
Hi! i am having problem to communicate between virtex4 fx60 to 512 SODIMM. I use the MIG1.6 to generate a controller. I add one module into the design, change some names and run ModelSim. The simulation looks fine. So, i use the ICE tools to get my bit file. When i check all the report, I saw the map report have th... 1 Oct 2006 12:00

MicroBlaze : Linkerscript for splitting the text block into 64kByte blocks
Hi all, I am implementing a microblaze processor in a subdesign in a Virtex4 component (ISE v7.1 sp3, EDK v7.1 sp2). The microblaze is using the internal BRAMS as instuction and data memory. The program is increasing and becomes more than 64kByte. The blockram controller does only support 64kByte size of mem... 29 Sep 2006 07:26

ISE Simulator Error 222: SuSE 10.1 Linux
Hi, i tried to simulate a small vhdl design with xilinx ISE (8.1 - 8.2 spxx, Webpack or foundation) running SuSE 10.1 linux, unfortunately there is an error. Because the VHDL code simulates with SuSE 9.2 I assume the code is fine and there are no spaces in the file path. Started : "Check Syntax". R... 26 Sep 2006 01:43