FPGA
in [Hardware]
|
crc code using vhdl found , few questions on it!!! Hello everyone, This link http://www.easics.be/webtools/crctool has the software to generate the vhdl code for the crc 32 polynomial. But the data bus width is only upto 256 bits. In the below code, crc is computed on only 4 bits of data. But i need to compute the crc on destination address, source address... 2 Nov 2005 17:41
Spartan IIE VHDL inout port bidirectional bus problem. Hi, I am trying to use a bidirectional bus, declared as inout in my vhdl code. When running on FPGA eveything works, except that bus. The bus is dead all the time and can not be read. I have tried changing that port to in only, and eveything works fine. I understand that for an inout port, tristate needs to ... 2 Nov 2005 03:11
Spartan-3E starter kit Any body knows when the Spartan-3E starter kit will be availaible from Xilinx? Website says 4th quarter. Isn't it 4th quarter already? ... 9 Nov 2005 21:41
.dat to .bit Hi all, I have this xess board which has a tool to initialise an SDRAM with data. I have 16-bit numbers that I want to load into the SDRAM. The tool needs .hex/.mcs format and I read that I need the promgen to convert from .bit to .hex. My question is how to convert from this .dat file (which is my input data f... 22 Oct 2005 18:45
EDK on Virtex4 FX using embedded ethernet MAC Hello I want to do a little EDK design that uses the embeded Tri-mode Ethernet MAC (TEMAC) of the Virtex4 FX parts. EDK offers several options for Ethernet MAC type but they are all soft MACs. The embedded MAC is a major selling point for me because of the logic saved and because compiling the soft MACs takes ... 24 Oct 2005 17:40
Xilinx USB cable Today I had a talk with the representant of Xilinx in russia. He adviced me to use Parallel cable 4 and not USB cable butwhen I asked why he told me that US Xilinx guys told him so. Can some one explain me? I need concrete examples. Perhaps he is only interested to sell ... one day he'll sell parallel cable ... an... 18 Oct 2005 17:13
Data2Mem usage - help required THIS IS IN CONTINUATION TO THE THREAD I MADE A COUPLE OF DAYS AGO. I WANTED TO ISOLATE THIS FROM THE OTHER STUFF, HENCE THE NEW THREAD: Refer here for the older thread: http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/ca8c05acec5703b3/a2502f9b088ecdea?lnk=raot&hl=en#a2502f9b088ecdea Hi, Here'... 19 Oct 2005 02:02
using i2c core hi, im trying to use i2c open source core available from opensorces.org and having problems with cofiguring the "scl" and "sda" from the top level design with the use of IO buffers. if anyone got experience on how to correctly configure these two ports from a top level hierachy, pls let me know. thank you. CMO... 25 Oct 2005 00:23
Error (XST): translate terminal to FCT Dear During synthesizing in XST of ISE 6.3, following error (?) is encountered.... Does anyone have experience on this trouble? Thankyou for information in advance ---------------- failed to translate terminal to FCT $n0133[7] = If $n0243 Then $n0297[7] If $n0245 Then $n0299[7] If $n0247 Then $n03... 16 Oct 2005 18:54 |