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JOP as SOPC component
The last days I played around with the Quartus SOPC builder [1]. Although I'm more a batch/make guy, I'm impressed by the easy to use tool. In order to scratch a little bit on the dominance of the NIOS II in the SOPC world I wrapped JOP [2] into an Avalon component ;-) So if you are interested to give a Java proc... 30 Aug 2006 08:01
Embedded clocks
I was posting to the thread on the embedded clock in a Manchester encoded bit stream and realized that the clock is not truely embedded in the data stream. I say this because you still have to know the clock rate in order for it to work. The decoder has to lock out the edge detection for the time between bits to ... 14 Aug 2006 22:13
Cyclone I & II memory fmax
Hi group, using a 128x32 bit simple dual port memory with independent read and write clock results in following fmax for both clocks (dout is registered): Cyclone (I) 256 MHz, Cyclone II 210 MHz (restricted) That's a little bit strange. Especially since the fmax for the memories in the data sheet is the... 6 Aug 2006 05:45
EDK : *.bit and *.elf Files
Hello Im working with the EDK and now I have got a question. At the moment I download the Hardware with the EDK and then I download and start the Software with the debuger. How can I load the Software and Hardware into the Flash, so that I can start run the system without the JTAG chain? With Impact I can only load th... 31 Jul 2006 10:19
Spartan 3E starter kit DDR SDRAM code
Has anyone VHDL code for accessing the DDR SDRAM on this Spartan 3E starter kit? -- Frank Buss, fb(a), ... 9 Aug 2006 13:44
component instantiation ISE7.1
hi, Iam trying to instantiate a component from my user_logic_ip.vhd : signal h:std_logic_vector(0 to 31); signal k:std_logic_vector(0 to 31); component inv port( x: in std_logic_vector(0 to 31); z: out std_logic_vector(0 to 31)); end component; begin call: inv portmap(h,k); iam giving these h... 27 Jul 2006 16:59
Problems simulation plb_gemac core for Virtex-II Pro
Hey there, I'm trying to simulate a design generated with EDK 7.1 that uses the plb_gemac core (version 1.01.a). When I try and load the design into Modelsim SE (using generate simulation hdl files, then export to proj nav, and using a testbench added to the proj nav project), the loading fails on the plb_gemac ... 31 May 2006 06:31
I2C on Xilinx V4
Well, I have a requirement for I2C or IIC communications to some video decoder chips on a new board I am designing. I would rather had not use this bus, but it seems that the Philips people have started a defacto standard in the video decoder world. So my questions are, what IO standard is best to use on a ... 26 May 2006 04:43
sqrt(a^2 + b^2) in synthesizable VHDL?
How do i calculate sqrt(a^2 + b^2) in synthesizable VHDL? The signals a and b are 32 bit signed fix point numbers (std_logic_vector (31 downto 0)). ... 12 May 2006 13:28
FPGA-based hardware accelerator for PC
If one wanted to develop an FPGA-based hardware accelerator that could attach to the average PC to process data stored in PC memory what options are there available. Decision factors are: + ease of use (dev kit, user's guide, examples) + ability to move data with minimal load on the host PC + cost + scalabilit... 25 May 2006 23:03
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