Xilinx Spartan3E Sample Pack 3rd party programing support now available
in [FPGA]
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From: Antti Lukats on 11 Jan 2006 04:11 as more and more customers are getting their Sample Packs so I decided to pre release the standalone programming utility for the board, available for immediate download http://xilant.com/component/option,com_remository/Itemid,53/func,fileinfo/id,8/ this has fully working base functionality for FPGA config and Flash programming. both for FPGA and Flash there is no need to worry about startup clock and for flash there is also no need to invoke and promgen or anything same .BIT files can be used for FPGA and Flash, the startup clock is automatically fixed to either JTAG of CCLK and the preparation for flash is also automatic startup clock auto-fix is now also supported in compressed bitstream (CRC is properly recalculated) only Cable III is supported for the moment, next releases may have wider hardware support included I have tried hard to also test out Xilinx suggested Flash programming for the sample pack (EDK, XMD, flashwriter.tcl) - I have failed so far, also completly failed have all attempts to use universal scan for the flash programming. nahitafu is using MITOU JTAG tool for flash programming of the sample pack but as that tool is not free and has no eval so our Flash programming utility for the Sample Pack is the first freely available and proven working solution to reflash the strataflash on the Sample Pack board. the base functionality of the tool is FREE of charge, there is no registration required, just download unzip and get start -- Antti Lukats http://www.xilant.com
From: Antti Lukats on 11 Jan 2006 11:40 [snip] > nahitafu is using MITOU JTAG tool for flash programming of the sample pack > but as that tool is not free and has no eval so our Flash programming > utility for the Sample Pack is the first freely available and proven > working solution to reflash the strataflash on the Sample Pack board. > > the base functionality of the tool is FREE of charge, there is no > registration required, just download unzip and get start > I just received a bit angry email from Nahitafu about my nonpolite wording about their products, so here is goes public appology to Nahitech, sorry ! additional info from Nahiteh: There will be no MITOUJTAG trial or evaluation versions available over internet, but a free evaluation of MITOUJTAG is offered for those who attend one of the upcoming trade shows in Japan. http://www.reedexpo.co.jp/inj/english/ there will be MITOUJTAG eval available, I wish I could go my 3 days visit to Tokyo is one of my best memories of all my travels. Sorry, Nahitafu - I did not mean to say bad about yours products I just think they are getting too little exposure in non-japanese speaking world. http://www.nahitech.com/jtag/basicv.html I dont find any english description any more, it used to be online also a evaluation version was available, what I have tested and it worked - the commercial version of MITOUJTAG is most likely much better than the very old version what was available as free version. Antti
From: Uwe Bonnes on 11 Jan 2006 12:47 Antti Lukats <antti(a)openchip.org> wrote: > I dont find any english description any more, it used to be online > also a evaluation version was available, what I have tested and > it worked - the commercial version of MITOUJTAG is most > likely much better than the very old version what was available > as free version. Missing english documents make MITOUJTAG hard to use... -- Uwe Bonnes bon(a)elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
From: Uwe Bonnes on 11 Jan 2006 12:51 Antti Lukats <antti(a)openchip.org> wrote: > as more and more customers are getting their Sample Packs so I decided to > pre release the standalone programming utility for the board, available for > immediate download > http://xilant.com/component/option,com_remository/Itemid,53/func,fileinfo/id,8/ > this has fully working base functionality for FPGA config and Flash > programming. > both for FPGA and Flash there is no need to worry about startup clock > and for flash there is also no need to invoke and promgen or anything > same .BIT files can be used for FPGA and Flash, the startup clock > is automatically fixed to either JTAG of CCLK and the preparation > for flash is also automatic startup clock auto-fix is now also supported > in compressed bitstream (CRC is properly recalculated) > only Cable III is supported for the moment, next releases may have > wider hardware support included Probably most of the Flash programming is already available in jtagtools: http://blackfin.uclinux.org/projects/jtagtools/ -- Uwe Bonnes bon(a)elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
From: Antti Lukats on 11 Jan 2006 13:03
"Uwe Bonnes" <bon(a)hertz.ikp.physik.tu-darmstadt.de> schrieb im Newsbeitrag news:dq3gip$v5i$1(a)lnx107.hrz.tu-darmstadt.de... > Antti Lukats <antti(a)openchip.org> wrote: >> as more and more customers are getting their Sample Packs so I decided to >> pre release the standalone programming utility for the board, available >> for >> immediate download > >> http://xilant.com/component/option,com_remository/Itemid,53/func,fileinfo/id,8/ > >> this has fully working base functionality for FPGA config and Flash >> programming. > >> both for FPGA and Flash there is no need to worry about startup clock >> and for flash there is also no need to invoke and promgen or anything > >> same .BIT files can be used for FPGA and Flash, the startup clock >> is automatically fixed to either JTAG of CCLK and the preparation >> for flash is also automatic startup clock auto-fix is now also supported >> in compressed bitstream (CRC is properly recalculated) > >> only Cable III is supported for the moment, next releases may have >> wider hardware support included > > Probably most of the Flash programming is already available in jtagtools: > > http://blackfin.uclinux.org/projects/jtagtools/ > defenetly not. the sample pack utility takes care of many aspects, namly in order to load the FPGA with flash programming IP core it may be required to set the Flash into read status mode, then trigger reconfig in parallel mode what is not seeing the signature - this will allow the JTAG port to be used to configure the FPGA. After that the flash-programming ip core can be used. if config signature is seen by FPGA at close proximity of where the parallal mode config starts then some tools like Impact, etc are not anymore able to configure the PFGA unless the config mode is changed away from BPI and power cycled. things like that are defenetly not handled by blackfin tools. they are also not handled by Impact or any other tool Antti |