Help! FIR Filter - MATLAB fdatool - VHDL
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From: Emel on 8 Jan 2006 11:21 Hi, I designed a 7th order FIR filter using MATLAB fdatool and obtained the VHDL code using the HDL Coder. I think that in the following part of the code there is a problem (Delay pipe line is an 8 element array, whose elements are 16 bit vectors. filter_in is a 16 bit vector): IF reset = '1' THEN delay_pipeline(0 TO 7) <= (OTHERS => (OTHERS => '0')); ELSIF clk'event AND clk = '1' THEN IF clk_enable = '1' THEN delay_pipeline(0) <= signed(filter_in); delay_pipeline(1 TO 7) <= delay_pipeline(0 TO 6); END IF; END IF; This part simply shifts previous inputs and should be saving the new input (filter_in) into delay_pipeline(0) (which it does). However, after delay_pipeline(0) <= signed(filter_in);, it says delay_pipeline(1 TO 7) <= delay_pipeline(0 TO 6);. As far as I know, the statements in a process are sequential. So, if you change delay_pipeline(0) right at the beginning, isn't the old value of delay_pipeline(0) totally gone? Because, afterwards delay_pipeline(0) (its new value) is assigned to delay_pipeline(1). I think that the order of the statements needs to be changed like: delay_pipeline(1 TO 7) <= delay_pipeline(0 TO 6); delay_pipeline(0) <= signed(filter_in); so that the seven previous inputs are stored in the array elements with indices from 1 to 7 and the new(current) input is stored in the element with index 0. I couldn't be sure. Can anyone help me? It is very crucial to me that I understand it correctly. Thanks in advance... Emel
From: Mike Treseler on 8 Jan 2006 14:28 Emel wrote: > I couldn't be sure. Can anyone help me? It is very crucial to me that I understand it correctly. In that case, I would get a vhdl simulator and test the code. -- Mike Treseler
From: backhus on 9 Jan 2006 02:45 Emel schrieb: > Hi, > > I designed a 7th order FIR filter using MATLAB fdatool and obtained > the VHDL code using the HDL Coder. I think that in the following part > of the code there is a problem (Delay pipe line is an 8 element > array, whose elements are 16 bit vectors. filter_in is a 16 bit > vector): > > IF reset = '1' THEN > delay_pipeline(0 TO 7) <= (OTHERS => (OTHERS => '0')); > ELSIF clk'event AND clk = '1' THEN > IF clk_enable = '1' THEN > delay_pipeline(0) <= signed(filter_in); > delay_pipeline(1 TO 7) <= delay_pipeline(0 TO 6); > END IF; < END IF; > > This part simply shifts previous inputs and should be saving the new > input (filter_in) into delay_pipeline(0) (which it does). However, > after delay_pipeline(0) <= signed(filter_in);, it says > delay_pipeline(1 TO 7) <= delay_pipeline(0 TO 6);. > As far as I know, the statements in a process are sequential. > So, if you change > delay_pipeline(0) right at the beginning, isn't the old value of > delay_pipeline(0) totally gone? Because, afterwards delay_pipeline(0) > (its new value) is assigned to delay_pipeline(1). Hi Emel, for instant relief follow Mikes advice and get yourself a simulator, you may need it anyway sometime. But to help you understand you should learn the difference between variables and signals in VHDL. Signals (assigned with <= ) are updated only at the end of each process. (look for Reader-Driver Model) Variables are instantly updated. What you said about sequential statements is right, but only affects signal assignments if you assign values to the same signal like this: Signal_1 <= '0'; if condition=true then Signal_1 <= '1'; end if; Here the first assignment serves as a default. The if-statement overwrites signal_1 whenever the condition becomes true. have a nice synthesis Eilert
From: Jon on 9 Jan 2006 08:08
From: "" <jonathan.a.clarke(a)gmail.com> Newsgroups: comp.arch.fpga Subject: Re: Help! FIR Filter - MATLAB fdatool - VHDL Date: Mon, 09 Jan 2006 05:04:35 -0800 Hi Emel, You could instead use Synplify DSP (http://www.synplicity.com/products/synplifydsp/) to generate either HDL or Verilog code for a filter design from a filter specification given to the fdatool in Matlab. The software is integrated into Matlab and allows you to develop more complex systems (which your filter could be a part of) for implementation on an FPGA using the block-based Simulink environment, and can generate code that is optimized for different FPGAs from both Altera and Xilinx. Best wishes, Jonathan |