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From: spartanius on 21 Nov 2006 16:49
I found the thread about this kit but cannot write there, since it is
more than 60 days old.

I am seeking for an empty or small project to start with the xilinx
ide. Of course I found the sample projects, but a) they are too complex
IMO (i do not need the pico blaze yet ) and b) I am having difficulties
in creating a complete and working project from out of the given files.

To be honest, I am afraid of using a wrong configuration - esspeciall
pin files - and then ruin my fpga!

So if anybody has an "empty" project with correct settings (like unused
pins z) and /or "z" definitions for the board (i think it is something
as an ucf) I was happy if he could send me that.

Thanks in advance

From: Frank Buss on 21 Nov 2006 17:13
spartanius(a)arcor.de wrote:

> To be honest, I am afraid of using a wrong configuration - esspeciall
> pin files - and then ruin my fpga!

You can copy the UCF definition from the PDF documentation and then set an
option (I forget which) in the IDE to ignore unconnected pins.

> So if anybody has an "empty" project with correct settings (like unused
> pins z) and /or "z" definitions for the board (i think it is something
> as an ucf) I was happy if he could send me that.

Not empty, but you can delete anything you don't need:

http://www.frank-buss.de/vhdl/spartan3e.html

Included on the web page: the non-intuitve steps required to synthesize it,
starting and use of iMPACT :-)

--
Frank Buss, fb(a)frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de
From: spartanius on 21 Nov 2006 18:07
thanks, but the synthesis sais "NgdBuild:755 - Line 7 in
'E:/xilinxprojekte/frankbuss/src/spartan3e.ucf':" for nearly all the
lines up to 200x. (?

From: Uwe Bonnes on 21 Nov 2006 18:24
spartanius(a)arcor.de wrote:
> thanks, but the synthesis sais "NgdBuild:755 - Line 7 in
> 'E:/xilinxprojekte/frankbuss/src/spartan3e.ucf':" for nearly all the
> lines up to 200x. (?

I also got there very elaborated messages on my design today. After digging
some time, I realized, that nets "LOC"ed in the UCF did not exist in the HDL
sources or had typing errors. But why the hell doesn't the error message
tell that?

--
Uwe Bonnes bon(a)elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
From: Frank Buss on 21 Nov 2006 22:17
spartanius(a)arcor.de wrote:

> thanks, but the synthesis sais "NgdBuild:755 - Line 7 in
> 'E:/xilinxprojekte/frankbuss/src/spartan3e.ucf':" for nearly all the
> lines up to 200x. (?

I can't reproduce this with the ise\Spartan3E.ise project file. If you've
setup your own project, right-click on "Implement Design"->"Translate" and
enable "Allow Unmatched LOC Constraints", if it is Uwe referenced. Do you
use the latest version of ISE (help->about: 8.2.0.3i) ?

Another interesting source of errors: ISE saves local settings for your
projects in C:\Documents and Settings\YourName\Local
Settings\Temp\something-with-ise-and-your-project-name
Once I replaced the source files for my project, because I didn't want to
setup all the settings again, but it didn't worked until I deleted the
temporary files.

--
Frank Buss, fb(a)frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de
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