Choice of Language for FPGA programming
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From: Jonathan Bromley on 7 Sep 2009 14:51 On Mon, 07 Sep 2009 12:46:38 +0100, Brian Drummond wrote: >I've tried to stay out of this language thread .. how'm I doing? <grin> At least we haven't started a slanging match yet. >> in the languages I've mentioned, concurrency is >>well-managed and easy to reason about. > >As VHDL successfully demonstrates. (I guess Verilog too, > [non]-blocking assignments apart) Well.... I'm not so sure. Verilog's concurrency model is like the Wild West - everyone is allowed to shoot from the hip any time they feel like it. Nonblocking assignments get you within reach of VHDL's model if you want it, but of course nothing is enforced. VHDL is OK - the loopholes are well-documented and few in number, and the discrete-event model works well enough for hardware modelling - but it's not easy to encapsulate process-to-process signalling protocols in an elegant way, and such signalling is not built in to the language and therefore you can't reason about it unless you've developed a calculus for whatever signalling protocol you choose to use. Of course, in practice much of this is obviated by the existence of standard interface protocols at various levels of any design - but it's kinda sad that we can't communicate between blocks by something as clean as my_output_channel!value ->->->-> my_input_channel?variable and be secure in our understanding of precisely what that means. Which brings us back to.... >Occam ... well it relied too heavily on a specific machine; >their fate was too closely connected. Commercially, of course, you're right. From a theoretical point of view, though, occam was just an implementation of CSP - which really does have a life of its own, and even has a live-and-kicking HDL based on it right now (Haste, from Handshake Solutions). >You can no longer coherently argue that Ada is too large, >complex, obscure or inefficient to be useful. Tee hee. It made me giggle when the C/C++ community, who had been whining for years about their dislike of the complexity of Ada and most particularly of generics, suddenly decided that templates were cool - and built a whole new pinnacle of complexity all their own. >Maybe - just maybe, there is a chance to improve software practice, >instead of bringing hardware practice down to its level. Seems to me that the two disciplines still have an awful lot to learn from one another. A bit more humility, on both sides, would do no harm. But, for sure, I will not be told by some Javascript-hacking weenie that I've been doing hardware all wrong for the past three decades. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley(a)MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.
From: ganeshstha on 2 Sep 2009 10:05 Hi, I am new to the FPGA world. I am using chipcon CC2400 board and has the Xilinx's XC2S200E FPGA. Is it possible to program it program the FPGA in C? I donot have any experience in VHDL and verilog. If it possible to program in C, what interface can i use? CC2400 has a 10 pin JTAG. any help will be highly appreciable.
From: Andy on 2 Sep 2009 10:34 FPGA's are not processors, so FPGA's are not "programmed" by a language per se. They are designed, and the design is specified using a schematic or a language, usually verilog or vhdl. "Programming" an fpga usually refers to downloading the design configuration data into the FPGA (i.e. via the JTAG port you mentioned. The FPGA and/or board vendor will provide utilities to "program" the FPGA with your design configuration data. The design configuration data is created by tools that read your design description (schematic or language-based), synthesize a netlist of various resources, and then optimally place and route those resources within the FPGA chip's architecture. With a lot of money for some high-dollar tools, it is possible to synthesize an FPGA design from a description written in the C language. Then you place and route that synthesized netlist using the FPGA vendor's tools (some available for free). But for starters, I would strongly recommend using an HDL like verilog or vhdl, and of those two, I recommend vhdl. Both are supported by the FPGA vendors' free design tools. Andy
From: James Harris on 2 Sep 2009 18:25 On 2 Sep, 15:34, Andy <jonesa...(a)comcast.net> wrote: .... > But for starters, I would strongly recommend using an HDL like verilog > or vhdl, and of those two, I recommend vhdl. Both are supported by the > FPGA vendors' free design tools. Verilog is closer to C and may thus be a little easier for the OP to learn. It's probably been covered many times but as a beginner myself it would be interesting to know why you recommend VHDL. Care to elucidate? James
From: Mike Treseler on 2 Sep 2009 19:33
James Harris wrote: > Verilog is closer to C and may thus be a little easier for the OP to > learn. Maybe, but it's harder to write C-like code because variables are not completely safe. -- Mike Treseler |