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From: Misiu on 18 Oct 2009 07:13
Hello,

I'm simulating a FSM written in Verilog using Xilinx ISim. Is there any
possibility to see in waveform the FSM state names instead of just
numbers, which I have to manually decode to state names?

Regards,
Misiu
From: Arlet on 18 Oct 2009 08:02
On Sun, 18 Oct 2009 13:13:39 +0200, Misiu wrote:

> Hello,
>
> I'm simulating a FSM written in Verilog using Xilinx ISim. Is there any
> possibility to see in waveform the FSM state names instead of just
> numbers, which I have to manually decode to state names?

I use a different simulator, but I usually do something like this:

`ifdef SIM

/*
* easy to read names in simulator output
*/
reg [8*6-1:0] statename;

always @*
case( state )
DECODE: statename <= "DECODE";
READ: statename <= "READ";
WRITE: statename <= "WRITE";
endcase

`endif

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