Controller to access internal FPGA registers from JTAG
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From: wzab on 16 Oct 2009 17:28 Hi, I just had to debug separately a system which usually works connected to the asynchronous parallel bus (address and data busses, read and write strobe). The system was connected to my development box via the JTAG interface (used to configure FPGAs), so I wanted to use the same interface to access the internal registers. I wanted a portable solution, working without any proprietary drivers. Therefore I have used the urJTAG + Python to implement the PC-side. The FPGA side for Xilinx chips has been written in VHDL, using the BSCAN_SPARTAN3 component, however it shouldn't be difficult to port it to Altera chips eg. using the code described here: http://groups.google.pl/group/alt.sources/browse_thread/thread/58acd8b31ea5bd0d (alt.sources "Python+urJTAG code to access Virtual JTAG in Altera FPGAs") I've implemented 3 types of the controller: jtag_bus_ctl_1.vhd - uses two instructions USER1 (to send address and R/W mode) and USER2 (to send/receive data) jtag_bus_ctl_2.vhd - uses only one instruction USER1 and single shift register to send both address+R/W mode and data. This one allows to optimize access by receiving the read data, when the next command is being sent jtag_bus_ctl_3.vhd - like version 2, but with "autoincrement" mode. You can send address once, and then read/write multiple data from consecutive addresses. The source code with more detailed description amd simple Python demos is available here: http://groups.google.pl/group/alt.sources/browse_thread/thread/38186c49dc5cf32e (alt.sources "FPGA internal bus controller driven by JTAG interface ") as PUBLIC DOMAIN code. (remember to select more_options->Show_original, when geting it from Google archive - othervise Python code indenting may be destroyed). I hope that this code may be useful for someone. -- Best regards, Wojtek |