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Wrong DDR communication
Hi everyone, I'm implenting a design on a Virtex4 that has to follow the communication of a processor with the ddr memory that is on the board. The board that I'm using is an Avnet ADS-XLX-V4LX-DEV160. The bridge that link the processor with the memory at the end has a Xilinx component IOBUF to transmit and receiv... 31 Mar 2010 12:05
result on hyperterminal is not displayed
Hi every body; i am working on xilinx EDK with MicroBlaze soft core processor. i am using Virtex 5 ML506 platform studio and my EDK is EDK 9.2 on this processor i am downloading C code for Elliptic curve diffie-hellman key exchange and it is done but result is not displayed on the hyperterminal so is there any body w... 6 Apr 2010 00:59
baud rates etc
Hi, I'm making a uart that will run at the standard baud rates and have a bit of a query, My board has a 50Mhz clk so I've used this to create a 1.8432Mhz clock then derive all the baud clocks from it,,eg, -- 50mhz/ 1843200 = 27.1267 -- 13 bit acc = 4096 msb -- divided by 151 -- 4096/151 = 27.1258 -- close e... 26 Mar 2010 16:43
where is VHDL-POSIX ?
Hello, A long time ago I have heard about VHDL-POSIX. however today, when I need it, the website is dead and nothing can be downloaded. What has become of this project and his maintainers? Is there anything similar ? Is there an old archive where I can read the... 28 Mar 2010 04:39
XST optimization
Is it possible to get a detailed report out of XST, listing the gates it has optimized out of a design? XST is removing some gates that I specifically put into a design, and I want to prevent this. I can use the XST constraints file, but I'd like to see exactly what it is doing. Googling hasn't turned up much,... 30 Mar 2010 08:17
USB 3.0 implementation on FPGA
Hi everyone, I'm just about to start an implementation of a USB 3.0 interface in VHDL for data transfer from FPGA to a PC and vice versa. The core should acts as a USB device for the PC. The core is intended for an FPGA projects where an "easy" interface to a PC is needed. Higher data rates as defined by the... 29 Mar 2010 03:39
Ring Oscillator -> counter differences
I have a 5 inverter ring oscillator, with its output being fed to a counter. This is run in a continuous process, that is to say it is run at 'gate speed', it is not clocked. I have an enable signal to activate the oscillator, which currently runs for 100ms. I can then clear the counter, and run it again, for 1... 27 Mar 2010 02:15
EMC discussion
As I think, many FPGA-designers have also to deal with EMC, I hope someone can help me here. We have currently some discussions (and doubts) regarding EMC-topics. As many people have different opinions on this subject, and it is quite hard to objectively verify, I would like to ask for some comments about following... 26 Mar 2010 17:52
PROM for Spartan 6 FPGA
Hi, I am planning to use a Spartan 6 FPGA (XC6SLX9) in my new design. Could someone suggest a reprogrammable PROM to configure this device, like the capacity of the Flash PROM needed ? ... 27 Mar 2010 09:32
Implementation of IWLS benchmark- Manual place and route
As I mentioned in another message, I am attempting to implement an IWLS benchmark on a spartan3e. I wrote definitions for all the undefined gates, and it now synthesizes just fine. However, I am attempting to manually place and route some main blocks in the design. When I go into PlanAhead, I do not see my ben... 24 Mar 2010 14:39
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