XST optimization
in [FPGA]
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From: Jason Thibodeau on 25 Mar 2010 15:06 Is it possible to get a detailed report out of XST, listing the gates it has optimized out of a design? XST is removing some gates that I specifically put into a design, and I want to prevent this. I can use the XST constraints file, but I'd like to see exactly what it is doing. Googling hasn't turned up much, yet. Thanks -- Jason Thibodeau
From: David Wiltshire on 25 Mar 2010 23:24 On Mar 26, 6:06 am, Jason Thibodeau <jason.p.thibod...(a)gmail.com> wrote: > Is it possible to get a detailed report out of XST, listing the gates it > has optimized out of a design? XST is removing some gates that I > specifically put into a design, and I want to prevent this. I can use > the XST constraints file, but I'd like to see exactly what it is doing. > > Googling hasn't turned up much, yet. > > Thanks > -- > Jason Thibodeau Not that I'm experienced but whenever I've seen a similar question (missing logic) it's been optomised out because you haven't connected the output to anything. Try connecting it to a pin out (even if that's not where you want it eventually) and see if it turns up. Dave
From: Jason Thibodeau on 26 Mar 2010 12:00 On 03/25/2010 11:24 PM, David Wiltshire wrote: > On Mar 26, 6:06 am, Jason Thibodeau<jason.p.thibod...(a)gmail.com> > wrote: >> Is it possible to get a detailed report out of XST, listing the gates it >> has optimized out of a design? XST is removing some gates that I >> specifically put into a design, and I want to prevent this. I can use >> the XST constraints file, but I'd like to see exactly what it is doing. >> >> Googling hasn't turned up much, yet. >> >> Thanks >> -- >> Jason Thibodeau > > Not that I'm experienced but whenever I've seen a similar question > (missing logic) it's been optomised out because you haven't connected > the output to anything. Try connecting it to a pin out (even if > that's not where you want it eventually) and see if it turns up. > > Dave Yes, I ran across that and I connected the output. Only the last gate in the design is being synthesized. All the other gates, which connect to it, are being optimized out. -- Jason Thibodeau
From: Jason Thibodeau on 28 Mar 2010 12:47 On 03/26/2010 12:00 PM, Jason Thibodeau wrote: > On 03/25/2010 11:24 PM, David Wiltshire wrote: >> On Mar 26, 6:06 am, Jason Thibodeau<jason.p.thibod...(a)gmail.com> >> wrote: >>> Is it possible to get a detailed report out of XST, listing the gates it >>> has optimized out of a design? XST is removing some gates that I >>> specifically put into a design, and I want to prevent this. I can use >>> the XST constraints file, but I'd like to see exactly what it is doing. >>> >>> Googling hasn't turned up much, yet. >>> >>> Thanks >>> -- >>> Jason Thibodeau >> >> Not that I'm experienced but whenever I've seen a similar question >> (missing logic) it's been optomised out because you haven't connected >> the output to anything. Try connecting it to a pin out (even if >> that's not where you want it eventually) and see if it turns up. >> >> Dave > > Yes, I ran across that and I connected the output. Only the last gate in > the design is being synthesized. All the other gates, which connect to > it, are being optimized out. > I'd like to bump this. Any word on how Ic an stop it from optimizing my required logic away? Why wouldn't Xilinx just allow me to turn off optimization? -- Jason Thibodeau
From: whygee on 28 Mar 2010 16:20
Jason Thibodeau wrote: > I'd like to bump this. Any word on how Ic an stop it from optimizing my > required logic away? Why wouldn't Xilinx just allow me to turn off > optimization? If you use VHDL, there are some "pragma" or "attribute"s ("set_dont_touch" or "keep" ?) that specify that a net must be kept. It worked for me on Actel/Synplify but I don't remember the syntax. I suppose that the same exists in Verilog. A quick googling told me (unchecked) : http://www.xilinx.com/itp/xilinx8/books/data/docs/xst/xst0059_8.html www.altera.com/literature/hb/qts/qts_qii51008.pdf and more, but I couldn't spend much time on this. HTH yg -- http://ygdes.com / http://yasep.org |