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From: Jason Thibodeau on 29 Mar 2010 12:40
On Mar 29, 4:37 am, Matthieu Michon <prenom....(a)gmail.com> wrote:
> On Sun, 28 Mar 2010 21:29:31 -0400
>
> Jason Thibodeau <jason.p.thibod...(a)gmail.com> wrote:
>
> (...)
>
>
>
> > I should have mentioned that I have tried all the iterations of keep
> > that I could think of, the gates are still being optimized out. I tried
> > both placing the keep attribute in the code, and using the xcf file,
> > neither have worked. I think part of the problem is I don't know hte
> > exact name of the nets being optimized out, since XST doesn't tell me
> > this information in the reports.
>
> Altough it is not universal, I use the "S" (save net flag) attribute for keeping signals from being optimized (typically for displaying them in Chipscope).
>
> The "S" attribute is described in the Constraint Guide (cgd.pdf).
>
> --
> Matthieu Michon <prenom....(a)gmail.com>

I'm having problems with my main machine, so I'm posting this from
google groups, I'm the OP.

I have some gates defined in a verilog file like this:

AND2X1 Gate1 (.A(net1) , .B(net2), .Y(net3));
INVX1 gate2 (.A(net3) , .B(net4));

etc..

The entities, AND2X1 and INVX1 are defined in a library, so they
synthesize just fine.

The final gate I have:
OR2X1 gate15 (.A(bla bla), .B(...), .Y(...));

This gate, gate15 shows up in manual place and route, but the others
connected to it do not. Why is that?

I'll look into the 'S' flag, thanks.
From: Muzaffer Kal on 29 Mar 2010 13:03
On Mon, 29 Mar 2010 09:40:40 -0700 (PDT), Jason Thibodeau
<jbloudg20(a)gmail.com> wrote:

>On Mar 29, 4:37�am, Matthieu Michon <prenom....(a)gmail.com> wrote:
>> On Sun, 28 Mar 2010 21:29:31 -0400
>>
>> Jason Thibodeau <jason.p.thibod...(a)gmail.com> wrote:
>>
>> (...)
>>
>>
>>
>> > I should have mentioned that I have tried all the iterations of keep
>> > that I could think of, the gates are still being optimized out. I tried
>> > both placing the keep attribute in the code, and using the xcf file,
>> > neither have worked. I think part of the problem is I don't know hte
>> > exact name of the nets being optimized out, since XST doesn't tell me
>> > this information in the reports.
>>
>> Altough it is not universal, I use the "S" (save net flag) attribute for keeping signals from being optimized (typically for displaying them in Chipscope).
>>
>> The "S" attribute is described in the Constraint Guide (cgd.pdf).
>>
>> --
>> Matthieu Michon <prenom....(a)gmail.com>
>
>I'm having problems with my main machine, so I'm posting this from
>google groups, I'm the OP.
>
>I have some gates defined in a verilog file like this:
>
>AND2X1 Gate1 (.A(net1) , .B(net2), .Y(net3));
>INVX1 gate2 (.A(net3) , .B(net4));
>
>etc..
>
>The entities, AND2X1 and INVX1 are defined in a library, so they
>synthesize just fine.
>
>The final gate I have:
>OR2X1 gate15 (.A(bla bla), .B(...), .Y(...));
>
>This gate, gate15 shows up in manual place and route, but the others
>connected to it do not. Why is that?
>
>I'll look into the 'S' flag, thanks.

My first take would be to simulate the design. If it does what you
need in simulation, then you might investigate if your design is
minimal in its specification. The synthesis is pretty accurate in what
it thinks the unnecessary parts of logic are so I'd check the design
very carefully before trying to keep gates which are really not
necessary for logic (as you seem to be mentioning mostly logic and not
buffers, inverters which might look unnecessaary but might be needed.)
--
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services

http://www.dspia.com
From: Jason Thibodeau on 29 Mar 2010 13:15
On 03/29/2010 01:03 PM, Muzaffer Kal wrote:
> On Mon, 29 Mar 2010 09:40:40 -0700 (PDT), Jason Thibodeau
> <jbloudg20(a)gmail.com> wrote:
>
>> On Mar 29, 4:37 am, Matthieu Michon<prenom....(a)gmail.com> wrote:
>>> On Sun, 28 Mar 2010 21:29:31 -0400
>>>
>>> Jason Thibodeau<jason.p.thibod...(a)gmail.com> wrote:
>>>
>>> (...)
>>>
>>>
>>>
>>>> I should have mentioned that I have tried all the iterations of keep
>>>> that I could think of, the gates are still being optimized out. I tried
>>>> both placing the keep attribute in the code, and using the xcf file,
>>>> neither have worked. I think part of the problem is I don't know hte
>>>> exact name of the nets being optimized out, since XST doesn't tell me
>>>> this information in the reports.
>>>
>>> Altough it is not universal, I use the "S" (save net flag) attribute for keeping signals from being optimized (typically for displaying them in Chipscope).
>>>
>>> The "S" attribute is described in the Constraint Guide (cgd.pdf).
>>>
>>> --
>>> Matthieu Michon<prenom....(a)gmail.com>
>>
>> I'm having problems with my main machine, so I'm posting this from
>> google groups, I'm the OP.
>>
>> I have some gates defined in a verilog file like this:
>>
>> AND2X1 Gate1 (.A(net1) , .B(net2), .Y(net3));
>> INVX1 gate2 (.A(net3) , .B(net4));
>>
>> etc..
>>
>> The entities, AND2X1 and INVX1 are defined in a library, so they
>> synthesize just fine.
>>
>> The final gate I have:
>> OR2X1 gate15 (.A(bla bla), .B(...), .Y(...));
>>
>> This gate, gate15 shows up in manual place and route, but the others
>> connected to it do not. Why is that?
>>
>> I'll look into the 'S' flag, thanks.
>
> My first take would be to simulate the design. If it does what you
> need in simulation, then you might investigate if your design is
> minimal in its specification. The synthesis is pretty accurate in what
> it thinks the unnecessary parts of logic are so I'd check the design
> very carefully before trying to keep gates which are really not
> necessary for logic (as you seem to be mentioning mostly logic and not
> buffers, inverters which might look unnecessaary but might be needed.)

I know the design intimately, and I know for a fact the gates it is
optimizing out are necessary for proper operation. I'm trying to figure
out WHY this is happening.

FWIW, this is not just a problem with Xilinx's optimization. Synopsys
does the same thing during synthesis, but I can tell it to not optimize.
The branches it is optimizing have a VERY (<.000001%) low probability of
activation, but I need the gates to remain, anyway.

--
Jason Thibodeau
From: Ed McGettigan on 29 Mar 2010 14:38
On Mar 29, 10:15 am, Jason Thibodeau <jason.p.thibod...(a)gmail.com>
wrote:
> On 03/29/2010 01:03 PM, Muzaffer Kal wrote:
>
>
>
>
>
> > On Mon, 29 Mar 2010 09:40:40 -0700 (PDT), Jason Thibodeau
> > <jbloud...(a)gmail.com>  wrote:
>
> >> On Mar 29, 4:37 am, Matthieu Michon<prenom....(a)gmail.com>  wrote:
> >>> On Sun, 28 Mar 2010 21:29:31 -0400
>
> >>> Jason Thibodeau<jason.p.thibod...(a)gmail.com>  wrote:
>
> >>> (...)
>
> >>>> I should have mentioned that I have tried all the iterations of keep
> >>>> that I could think of, the gates are still being optimized out. I tried
> >>>> both placing the keep attribute in the code, and using the xcf file,
> >>>> neither have worked. I think part of the problem is I don't know hte
> >>>> exact name of the nets being optimized out, since XST doesn't tell me
> >>>> this information in the reports.
>
> >>> Altough it is not universal, I use the "S" (save net flag) attribute for keeping signals from being optimized (typically for displaying them in Chipscope).
>
> >>> The "S" attribute is described in the Constraint Guide (cgd.pdf).
>
> >>> --
> >>> Matthieu Michon<prenom....(a)gmail.com>
>
> >> I'm having problems with my main machine, so I'm posting this from
> >> google groups, I'm the OP.
>
> >> I have some gates defined in a verilog file like this:
>
> >> AND2X1 Gate1 (.A(net1) , .B(net2), .Y(net3));
> >> INVX1 gate2 (.A(net3) , .B(net4));
>
> >> etc..
>
> >> The entities, AND2X1 and INVX1 are defined in a library, so they
> >> synthesize just fine.
>
> >> The final gate I have:
> >> OR2X1 gate15 (.A(bla bla), .B(...), .Y(...));
>
> >> This gate, gate15 shows up in manual place and route, but the others
> >> connected to it do not. Why is that?
>
> >> I'll look into the 'S' flag, thanks.
>
> > My first take would be to simulate the design. If it does what you
> > need in simulation, then you might investigate if your design is
> > minimal in its specification. The synthesis is pretty accurate in what
> > it thinks the unnecessary parts of logic are so I'd check the design
> > very carefully before trying to keep gates which are really not
> > necessary for logic (as you seem to be mentioning mostly logic and not
> > buffers, inverters which might look unnecessaary but might be needed.)
>
> I know the design intimately, and I know for a fact the gates it is
> optimizing out are necessary for proper operation. I'm trying to figure
> out WHY this is happening.
>
> FWIW, this is not just a problem with Xilinx's optimization. Synopsys
> does the same thing during synthesis, but I can tell it to not optimize.
> The branches it is optimizing have a VERY (<.000001%) low probability of
> activation, but I need the gates to remain, anyway.
>
> --
> Jason Thibodeau- Hide quoted text -
>
> - Show quoted text -

The raison d'être of HDL synthesizers is to produce an optimized
design that matches the HDL input code. If the tools didn't do this
then they no one would use or buy them.

If the gate/net was optimized away then it wasn't needed. Either the
input (registers and IO pads) equation cone had redundancies or there
was a redundancy to the final output (registers or IO pads). The
synthesizer will also move the equations around to optimize timing. A
signal that you have coded to appear early in an multi-level logic
cone may be pushed to later in the logic cone to improve the timing.

If the synthesizer changed the logic then it would be a bug. Since
you have said that this happens in two different tools it is very
unlikely to be a bug.

I think that you mentioned that you had OR'ed all of the outputs
together to keep all of the logic from being trimmed. I would suggest
instead that you register all of the outputs and then OR the registers
outputs to keep the logic. Optimizing across the register boundaries
is available in some synthesizers, but there is usually an option to
enable/disable the feature.

Ed McGettigan
--
Xilinx Inc.

From: Rob Gaddi on 29 Mar 2010 14:47
On Fri, 26 Mar 2010 12:00:31 -0400
Jason Thibodeau <jason.p.thibodeau(a)gmail.com> wrote:

> On 03/25/2010 11:24 PM, David Wiltshire wrote:
> > On Mar 26, 6:06 am, Jason Thibodeau<jason.p.thibod...(a)gmail.com>
> > wrote:
> >> Is it possible to get a detailed report out of XST, listing the
> >> gates it has optimized out of a design? XST is removing some gates
> >> that I specifically put into a design, and I want to prevent this.
> >> I can use the XST constraints file, but I'd like to see exactly
> >> what it is doing.
> >>
> >> Googling hasn't turned up much, yet.
> >>
> >> Thanks
> >> --
> >> Jason Thibodeau
> >
> > Not that I'm experienced but whenever I've seen a similar question
> > (missing logic) it's been optomised out because you haven't
> > connected the output to anything. Try connecting it to a pin out
> > (even if that's not where you want it eventually) and see if it
> > turns up.
> >
> > Dave
>
> Yes, I ran across that and I connected the output. Only the last gate
> in the design is being synthesized. All the other gates, which
> connect to it, are being optimized out.
>

This may be a silly question, but exactly what does the logic that's
being optimized out do?

--
Rob Gaddi, Highland Technology
Email address is currently out of order
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