First  |  Prev |  Next  |  Last
Pages: 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
Xilinx Pipelined/Streaming FFT Architecure?
I guess Xilinx also uses R2^2SDF --- because they have scaling for every pair of radix 2 butterflies. Altera clearly mentions that their pipelined FFT core uses R2^2SDF architecture. But I could not find any such info about Xilinx -- can anyone help? Onkar Hi, Can anyone tell me whether t... 20 Apr 2010 15:41
Xilinx Virtex-4 Block RAM Initialisation missing
Hi people. This problem has been driving me batty now for a while. I have spent ages tracking down a bug in my VHDL only to find there is no bug at all - just that the initialisation data I have pre-set into a VIRTEX-4 BRAM does not appear to be there after the FPGA has been loaded. I have tried a number of diff... 18 Apr 2010 18:36
Which 32 bit cores support full Linux?
My customer was talking about running PC Linux on a CPU in an FPGA. I believe the one big requirement is that there has to be a MMU. Which of the three FPGA vendor's cores are available with a Linux supported MMU? I cores I know about from vendors are uBlaze, NIOS and LM32. I don't think Actel has one, they see... 20 Apr 2010 15:41
Microblaze and DDR2
I am trying to integrate my own DDR2 controller into a Microblaze processor. I have created a board support package file with the ports defined and have added an IOTYPE attribute of XIL_MEMORY_V1. However when I run the bsb it thinks that I want to use the Xilinx MPMC. Maybe I shouldnt be adding this attribute, but I n... 17 Apr 2010 11:51
Changing output pins slew&drive strength without re-run ISE processes?
Hi all, Is there anyway to modify bit file just to change I/O slew rate & drive strength without re-run ISE processes ? TIA & TGIF ... 17 Apr 2010 11:51
Clock Mux by software ...
Hi, I have Spartan 3A DSP 3400. My board have two clocks, first clock is TXCO, sencond clock is VCXO+PLL generator with external reference. The two clocks have the same frequency. I wondered how it is possible to exchange via software between the two clocks on Microblaze while the software is running, without ca... 16 Apr 2010 09:26
Implementing bidirectional bus inside the FPGA
Hi all, I would like to implement a router mesh (3x3) with bidirectional links within the FPGA . I am using a Virtex 4 board. Since there are a lot of bidirectional buses in my design, I would like to know if it is possible to implement all the buses using tristate logic? when I snthesised only one single bid... 15 Apr 2010 22:33
Read from the compact flash
Hi, I'm going to use the compact flash as a store unit. It wouldn't have any filesystem format. I will copy raw binary data to it starting from the first sector. Then the objective is to read this data from the compact and then copy it to the fpga memory in order to use it to feed my design. Can somebody gi... 20 Apr 2010 15:41
EDK BFM Simulation
Has anyone managed to get access to the BFM simulation package. For some reason I keep getting denied. Jon --------------------------------------- Posted through ... 14 Apr 2010 04:23
Nios Memory Protection Unit
Hi, is anyone out there using the Memory Protection Unit option in the Nios II processor from Altera? I am trying to use it in a simple system with no OS and would like to know if it has been used before by someone else to help to asses if the problems I am having are on my own code or if I can blame the MPU impl... 13 Apr 2010 09:25
First  |  Prev |  Next  |  Last
Pages: 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42