Altra mega core SDI vs. Gennum devices
Hi all, Which one's better to invest in the next project ? TIA and TGIF ;-) ... 14 May 2010 12:47
2 New issue of Xcell Now available
My small but mighty team has recently issued two new issues of Xcell Journal magazine. The first is our 2010 Customer Innovation issue of Xcell, which features profiles of 20 customer designs. The latest issue is the Spring issue of Xcell, which features a cover story on the new ARM-MPU core device architecture and... 13 May 2010 20:28
problem in clock input in virtexpro/spartan3a/spartan3 kit
hi In virtexpro/spartan3a/spartan3 kit when we using system clock(100Mz/50Mhz) and take this clock on i/o pin(by writing VHDL program) on digital C.R.O. it will show corrupred signal , I also tried this by DCM CORE GENERATOR again it is giving wrong o/p. Can anybody suggested me solution of this problem. ... 14 May 2010 19:23
Xilinx Synthesis Tool generates clock signals from combinatorial logic
Hello, I am facing a problem of clock signals being generated by combinatorial logic. Here is the timing report: TIMING REPORT NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE. Clock... 19 May 2010 10:25
New 'standard' compact programming header needed!
15 years ago a 2x5 pin 0.1" pitch through hole programming header wasn't excessively large, these days it's a bit of a joke, worse if you use a surface mount part. It would be good to have a more compact 'standard' surface mount programming header. I've used Molex Picoblade vertical headers and connectors reas... 19 May 2010 18:14
ModelSim XE III error
Hi all i'm suing ISE 11.4 and ModelSim XE III when i do the behavioral simulation it works well but when i do the post place & route simulation the ModelSim report this errors "# ** Error: netgen/par/fpu_double_timesim.vhd(45842): (vcom-1141) Identifier "x_dsp48a1" does not identify a component declaration." h... 11 May 2010 15:37
what is the fmax of the simple dual port ram in the altera fpga
I used the simple dual port ram in quartus with the altera fpga,but when i simulate it in 100Mhz, the read data isn't what i haved writen in. but the classic timing analyzer shows the fmax is about 200Mhz.could anybody help me. I am so bothered with it. --------------------------------------- Posted ... 12 May 2010 06:56
Expecting sequential output, but RTL shows concurrent implementation.
> Sorry for hijacking the thread, but... do you mean that if I write this code: signal foo : std_ulogic_vector(3 downto 0) := "1010"; I would *not* normally expect the FPGA to power up with "1010" in the signal!? I've only ever worked with Xilinx FPGAs using ISE, so I assumed it worked everywhere; is thi... 18 May 2010 13:38
Two PCIe Endpoints in one Virtex-6?
Hello, I had a look into the V6 Datasheets, but couldn't find a direct clue. Would it be possible to implemement two PCIe Endpoints in one Virtex-6 FPGA? Most of the V6-Devices offer two hard PCIe blocks and the PCIe root device should initiate link training on all lanes. If I understand this correctly, it shoul... 14 May 2010 07:19
Register Now: FPGA Camp Bangalore, INDIA. May'21
I am pleased to announce the next upcoming FPGACamp to be held on May'21, 2010. The registration for the event is completely FREE. You can RSVP by visitinghttp://events.linkedin.com/FPGA-Camp-Bangalore-India/pub/281752 orhttp://www.fpgacentral.com/fpgacamp FPGA Camp is the 1st and only open source FPGA conference... 11 May 2010 02:26