Advice on Xilinx Spelunking
I've got a Spartan 6 design that I'm working with under ISE 11.5. A code block that I would expect to take up about 200 LUTs is taking 800 instead. 600 LUTs wouldn't be the end of the world, except I'm planning to replicate this block 32 times, which puts me well over the top. So the question becomes where a... 28 May 2010 19:15
Hi, how does an (unclocked) 2:1 multiplexer behave if input B is selected and input A becomes metastable ? Does the metastability of A have an influence on the stability of the mux output at any point of time ? cheers, hssig ... 25 May 2010 16:50
Extended deadline (15 July 2010): CACS Singapore [EI Compendex,ISTP,IEEE Xplore]
[ Please forward to those who may be interested. Thanks. ] ================================================================== 2010 International Congress on Computer Applications and Computational Science CACS 2010 http://irast.org/conferences/CACS/2010 4-6 December 2010, Singapore ==============================... 24 May 2010 00:27
About CLB inter-slice communication in Virtex
In the Virtex 4 FPGA, slices within a CLB are interconnected with each other. However, in Virtex 5 and Virtex 6, there is no direct connection between slices of a CLB. Why was this change made? Thanks --------------------------------------- Posted through http://www.FPGARelated.com ... 24 May 2010 07:56
Do Xilinx really want people to report INTERNAL_ERRORs?
.... because it certainly seems like they don't. A couple of minutes ago, I made some changes to my project which made the synthesizer fall flat on its face: INTERNAL_ERROR:Xst:cmain.c:3464:1.56: Process will terminate. For technical support on this issue, please open a WebCase with this project attached at... 23 May 2010 20:07
Xilinx Xact software for XC2018 Logic Cell Array
I bought a few of these on ebay but I cant find Xilinx Xact software needed to design with these FPGAs Can someone point me in the right direction? Anyone have a copy I can buy? sincerely hungry student ... 25 May 2010 17:56
Last Xilinx Webpack that was big-brother free?
Call me a sadist, but I tend to cruise through the license agreements and EULAs before installing software to make sure I'm not being victimized by using someone's application. I wanted to bring my S3E starter kit back up to prototype Xilinx-based algorithms while employed by a particularly Altera-friendly group. ... 30 May 2010 11:05
Any V6's available?
Does anybody have any XC6V130T-2FFG1156CES's available? Even used on a boad would be acceptable. I don't think the non-ES parts have been released yet... ... 21 May 2010 19:26
can I do image processing using 8bit color output FPGA board?
Hi, I have a Spartan 3E FPGA starter board of 100K gates. I just want to do some basic image processing such as dead pixel correction(I just use black&white images), there is only 8 bits color output and only a Flash ROM embedded. I want to read RAW format file in which includ the pixel information, after simple pr... 21 May 2010 22:42
Xilinx / Altera
I am looking for the following Xilinx & Altera pre-fixes to purchase if anyone has any extra in their inventory: EP2S... EP3S.. XC5V.. XC4V.. Any qty's. Please advise - Thank you ! ... 21 May 2010 10:34