FPGA

Xilinx MIG v2.3 Spartan3A-DSP DDR2 Interface
Hey everyone, I have been struggling to use the MIG to generate a memory interface to the DDR2 device. First some background info: I am using the Xilinx® Spartan®-3A DSP XtremeDSP™ Starter Platform. I am using ISE 10.1 with MIG v2.3. I have created the MIG from GUI and played around with it. I also edited the... 28 Apr 2010 15:07

Virtex 4 ICAP partial reconfiguration
I have built a design with PR flow 9.2 using bus macros. The dynamic reconfiguration works using Impact and downloading the partial bistreams. I have connected the Virtex 4 ICAP port to the LEON3 processor through the AMBA APB bus. I would like to perform partial reconfiguration through ICAP. I have a C software... 26 Apr 2010 09:07

Craignell2-48 - 48 Pin FPGA DIL Module
To complete a busy week of new boards a picture of our new 48 pin FPGA DIL module - Craignell2-48 is now on http://www.enterpoint.co.uk/component_replacements/craignell2.html. We have these with us to show at ESC in San Jose this week.for anyone going to that event and wants to see and hold them. John Adair En... 27 Apr 2010 13:18

Helping tools
Hi Perhaps this is just newbie question, but I'm looking for tool helping me with bits. The point is that I can't find it and I don't know if there is something out there or the usage is so trivial for everybody used to hardware design thinking so nobody bothered to create something like that. If there is nothing t... 25 Apr 2010 13:15

Absolute value of a two's complement number
Hi, I'm trying to calculate the absolute value of a signed number (two's complement). Right now, I sign extend the input, and when msb=1, inverse all bits and add 1. The sign extend is to take care of the most negative number. Is there a better way in terms of hardware utilization? Here is my verilog code... 23 Apr 2010 20:38

Quartus II under Windows7?
My XP box died the other day and was replaced by a 64 bit Windows7 machine. Now my $%^&Quartus II software won't run, and Altera says Win7 ain't supported. Anybody know of a workaround? I'm developing on the Altera Cyclone III FPGA on the Altium Designer NanoBoard 3000. Thx, Bob ... 30 Apr 2010 13:56

Tutorial for C based bit-accurate hardware modeling ?
I am a student who is trying to model a parallel hardware architecture for FFT using a C. My aim is to verify the correctness of my architecture and also estimate the noise introduced when fixed point is used. Is there any tutorial/book or any help that can guide me in this process of C modelling --- and especial... 23 Apr 2010 20:38

Synplify synthesis error
Hello everyone, I'm trying to synthesise my design using Synplify Pro D-2010, but I am new to this tool and encountering various problems. Here's my first one, which I'd like to solve to be able to investigate other mysterious errors I'm getting. In my design, I use a package called "types_viterbi". In my VH... 26 Apr 2010 12:35

multiboot spartan3E
I will use Intel StrataFlash Parallel NOR Flash PROM to store two . bit files I have been able to generate the two files. prm &. mcs after having 1) prepare a PromFile. 2) Prom supporting multiple Design versions . 3) Adding the first and the second Bitsream bitsream after that I want to configure the paral... 23 Apr 2010 20:38

Polmaddie Family CPLD and FPGA Teaching Boards
We finally made an assembly slot and built the 4 remaining Polmaddie CPLD and FPGA boards. These very low cost CPLD and FPGA boards will sell to universities and colleges in prices as low as $30-40. One off pricing starts at $60-70. The concept is a bit different to that offered by most development board vendors... 23 Apr 2010 20:38