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From: dlopez on 21 Apr 2010 22:26
Hi,
I'm trying to calculate the absolute value of a signed number (two's
complement).

Right now, I sign extend the input, and when msb=1, inverse all bits and
add 1. The sign extend is to take care of the most negative number.

Is there a better way in terms of hardware utilization?


Here is my verilog code:

wire signed [w-1:0] a;
wire signed [w:0] b, c;

assign b = $signed(a); //sign exted input
assign c = b[w] ? (~b+1'b1) : b; //inverse all bits and add 1 if msb=1

Thanks,
Diego

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