FPGA
in [Hardware]
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Job experience? How? Hello, I am a third year student, but interested in FPGAs and linking my future with this area of electronics. To have a point of view of my future, I've browsed some job search pages using "FPGA" in search field. However almost all of the offers are for "FPGA seniors", experience not less that ~5 years. How can I... 3 Jun 2010 13:23
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Graphical User Interface project on Spartan-3 FPGA I am a student of Electronics and I am going to do semester work on the topic "Implementation of Graphical User Interfaces on an Embedded Platform". We are allowed to choose a project of our own so this is why I am currently looking for suitable project ideas. The work shall be implemented on a Xilinx Spartan-3... 2 Jun 2010 05:27
Virtex 7? >On 21 Apr., 18:15, Ed McGettigan <ed.mcgetti...(a)xilinx.com> wrote: On Apr 20, 6:20=A0pm, "stephen.cra...(a)gmail.com" <stephen.cra...(a)gmail.com> wrote: The CTO of Xilinx, during his keynote this morning at the Reconfigurable Architectures Workshop in Atlanta, made mention of the recent anno... 31 May 2010 08:39
Effect of fanout on route delay (Spartan3) Hi, The Spartan3 datasheet is very light on the topic of interconnect. I wonder how big the effect of fanout is, on the delay of a route. I'm not talking about "high fanout" signals like CLK, but rather just normal logic signals. For example, in a design I can choose to use fanout=5 (easy), or fanout=4 (wit... 31 May 2010 14:09
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Estimating resource utilization of cores (from Xilinx CoreGen) Hi, How can I estimate the resoures used by a core generated by CoRE GEn ---- I guess the resource utilization report should give this right? What do the percentages in the resource utilization report of CoreGEN indicate --- is it the percentage of total FPGA resource OR is it percentage with respect to ... 30 May 2010 16:29
Anyone else need bigger parts in small (low pin count) packages I am looking at reducing the cost of a board while improving the performance and one way is to add a processor to offload the low bandwidth portions of an FPGA design and then reduce the capacity of the FPGA. Using an FPGA with 5 volt tolerant I/Os will let me remove a couple of quick switch parts as well. This h... 18 Jun 2010 19:03
Programming Digilent Nexys 2 from Linux A while back, Andy Ross posted a Perl script that pulls together the many steps required to program a Digilent Nexys2 board under Linux: http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/c7557a7b4bc9900c I just wanted to let everyone know that this script, along with the firmware it uses, is ho... 3 Jun 2010 00:12 |