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Binary integer to ASCII string in HDL?
I need to do some fast (<5 usec) conversions of binary integer to ASCII string in HDL (NIOS, FPGA, etc) - basically a fast substitute for sprintf(s,"%d",n); Does anyone know if: 1. It's practical to make an effort to do it in HDL or will it be an endless rats hole? 2. Is there an IP vendor that can sell it... 30 Jun 2010 17:34
fooling the compiler
We have a Spartan6/45 that's talking to 16 separate SPI A/D converters. The data we get back is different, but the clock and chip select timings are the same. To get the timing right, avoiding routing delays, we need our outgoing stuff to be reclocked by i/o cell flipflops. So what happens is that we have on... 3 Jul 2010 14:34
I have helped support many of the users of this group with long lead time, allocation and obsolete parts. The support usually starts off with FPGA 's, but has led into other many other semiconductors and LCD panels. I am seeing lead times being pushed out by most manufactures and in most cases will be able to suppl... 24 Jun 2010 14:07
Please suggest NON Volatile FPGA Devices
Hi Group, Could you guys please recommend me a non volatile fpga (which can hold its bit stream in, an on-chip flash). I might need to put a soft core cpu in the fpga as well. so a medium size device like Spartan-3AN-700 will be fine for me. I am looking for any device which is smaller in size than Spartan-3AN-7... 24 Jun 2010 19:41
Help with VGA controller in Verilog
I've been trying to code a simple VGA controller to run on my Altera DE1 board. You can see my code here: Note that my board has a DAC which converts the 4-bit digital signal for each of the RGB colors to the analog signal required by VGA. The timings are as found here for exam... 24 Jun 2010 19:41
Spartan-3E starter kit USB schematics ? (again)
On the Xilinx Spartan-3E Starter kit board there is an USB interface to program the FPGA chip via JTAG. However this part of the schematics is missing from the documentation: I remember that someone actually did locate the connections around 20... 23 Jun 2010 12:49
altshift_taps for Xilinx?
Hi all, I'm developping a firmware using Xilinx FPGA spartan3, I want to use an FPGA core which has the same functionality as altshift in Altera FPGA, I was thinking about using FIFO but I need to implement 4 taps. Anyone knows well about Altera and Xilinx could help me please? Thank you !! ... 1 Jul 2010 07:44
Question about Altera NIOS II, Eclipse, Quartus subscription try version 9.1
Hi, I am new to Altera Eclipse for quartus subscription 9.1 version. I want to learn NIOS programming. I go through the simpliest version on 'Getting Started' part in "Nios II Software Developer's Handbook". I create a project step by step according to the handbook (I have no NIOS II evaluation board at home). T... 22 Jun 2010 22:38
Polmaddie Low Cost CPLD/FPGA Boards Update
There are now new user manuals and schematics for Polmaddie1, Polmaddie2 and Polmaddie3 boards. Polmaddie4 and Polmaddie5 to follow shortly. Jump page to all of these boards John Adair Enterpoint Ltd. ... 22 Jun 2010 16:01
SDRAM capacity using Petalinux
Hi, I successfully ported Petalinux on the XUPV5-LX110T FPGA board using 8 KB of Data/Instruction Cache. My SDRAM is 256 MB (MT4HTF3264HY-667F1). However when I create a file (vi myFile) at the /var/tmp location, myFile cannot be bigger than 25 MB otherwise Petalinux will complain that my system is out of memory and i... 23 Jun 2010 18:24
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