FPGA
in [Hardware]
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USB3.0 device detection how does a host know a usb3.0 device get attached?what kind of reset will the host give on detecting the device --------------------------------------- Posted through http://www.FPGARelated.com ... 29 Jul 2010 07:28
please help and advice : Error: Pack:1107 - Unable to combine the following symbols into a single IOB component: On Jul 28, 7:47 am, Eyyub Can Odacioglu <ecodacio...(a)gmail.com> wrote: How can I solve this error? ERROR:Pack:1107 - Unable to combine the following symbols into a single IOB component: BUF symbol "TXD_OBUF" (Output Signal = TXD) PAD symbol "TXD" (Pad Signal = TXD) Each of ... 28 Jul 2010 14:03
problem in loading from flash to spartan-3 xc3s200 Hello, I'm learning to use FPGA, and i've designed and realized some schematic using spartan-3 xc3s200 (208 pin) and xcf01s, the last following UG332.pdf pag 68. I'm using the xilinx ise 9.2 updated sp4, and a digilent programmer like xilinx programmer. In impact, the .bit and the mcs file was correctly creat... 28 Jul 2010 14:03
Overheated FPGA? (Spartan-3E) Me and my college are first time users of programming a FPGAs. We have bought the already assembled card Xylo-L from knjn. It has a Spartan-3E FPGA among other parts. Somewhere during the process of handling this card something has gone wrong and now when we connect power to the card it gets really hot fast. We can sti... 28 Jul 2010 16:15
please help and advice : Error: Pack:1107 - Unable to combine the following symbols into a single IOB component: How can I solve this error? ERROR:Pack:1107 - Unable to combine the following symbols into a single IOB component: BUF symbol "TXD_OBUF" (Output Signal = TXD) PAD symbol "TXD" (Pad Signal = TXD) Each of the following constraints specifies an illegal physical site for a component of type IOB: ... 28 Jul 2010 08:31
Getting started with partial reconfiguration Hi, I wanna get started to design architectures with partially reconfiguarable modules. I am using a Virtex-5, according to the manual this board now also allows to dyanmically change the clock using the DRP port. The way to implement partially reconfigurable logic blocks seems to be described in this document... 29 Jul 2010 11:51
RS-Latch Hey, I have to implement a RS-Latch. I know that it is not a good design practice but because of limited clocks, I have to use it. Now my concerns are that this latch could go metastable. In my design, the reset and set input of the latch are not set simultaneously. But before the set input there is a AND gate w... 27 Jul 2010 19:28
LPM_MULT issues I haven't used Altera tools for ages, but I'm working on a Cyclone 3 design now, so I'm trying to understand them. The design is going to use many 20x20 signed multipliers. I had hoped that the synthesizer would be able to infer a 20 x 20 that used one 18 x 18, and did the rest in fabric, but I couldn't get that... 27 Jul 2010 15:02
All Digital PLL Hey Folks, I am trying to implemented an all digital PLL on Xilinx FPGAs. First, I wrote some Matlab code to see the functionality of the PLL. Everything seemed to work fine. Then I quantized the operations in Matlab to find out the amount of precision I need in hardware. That's when the PLL stopped working, or ... 27 Jul 2010 21:41
Problems with VHDL lookup table in Quartus Hi, I'm trying to debug a Cyclone design which writes values taken from a lookup table to the address inputs of a crosspoint analog switch. The problem is that everything looks OK in the Quartus simulator, but when I test the design on the target hardware it seems to be pulling the wrong values out of the LUT. ... 30 Jul 2010 11:51 |