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how to store data in i2c slave
Hi all, I'm implementing an i2c core using FPGA to build interface between DSP and sensors, the objective is to configure the sensors using i2c bus, FPGA first acts as i2c slave and receives all the register data from DSP, then switch as i2c master to send duplicates of register data to several sensors(each sens... 2 Aug 2010 14:44
DMA operation to 64-bits PC platform (continued)
Hi, I have a custom made PCIe board with a Virtex 5 FPGA on which I implemented a DMA unit which uses the PCIe endpoint block plus v1.14. I also implemented simple read/write operations from the PC to the board (the board responds with completion TLPs). The read/write operations are working, DMA is not working (... 11 Aug 2010 12:31
Modify UCF file generated with MIG
Hallo, I have just created a driver for a DDR2 working with a Virtex 5 FX30T. I want to add this driver to a bigger project but I do not know very well how to modify the constrains file in order to make it work. I have made some hierarchy modifications to the file but I do not really get what should I modify..... 2 Aug 2010 16:56
Differences between Verilog versions
On Sun, 1 Aug 2010 01:06:16 +0000 (UTC), Giorgos Tzampanakis wrote: Where can I find a listing of the features that were added to Verilog in the 2001 version, and then of the ones added in SystemVerilog? It's surprisingly hard to extract that information. IEEE standards conventions strongly discourage the... 4 Aug 2010 22:20
FX12 mini module with EDK 10.1
Hi every one I need to implement 100Mb ethernet connection on FX12 mini module for data transmission only. EDK 10.1 XPS Base System Builder gives me two options for ethernet connection (using powerPC) for memec FX12 mini module development board. Either use XPS LL TEMAC or XPS ETHERNET LITE. Can anyone kindly te... 1 Aug 2010 00:51
Spartan 3E: SPI programming through JTAG
I have an embedded design based on Spartan 3e and I need to be able to update it. Impact is not an option for lack of Xinlinx cables in the field and also because it has become a behemoth since its first version. :( I have a simple adapter that allowed me to update a CPLD by connecting the PC serial port to the JTA... 31 Jul 2010 20:32
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100% free dell laptaps offerd by dell and Vodafone companies. great offer….free dell laptops …no need money, no need shipping charges…absolutely free… i have hidden the full details in an ” BIG IMAGE” at the”Top Of My Blog.” click that ” big image” and get dell laptap 100% free… my blog is http://human... 31 Jul 2010 02:09
DSP with sensor i2c interface
Hi all, I have to interface DSP with 3 image sensor,s there're only two i2c GPIO for DSP, so I need to implement an i2c core in FPGA, I've implemented an i2c slave core to receive data from DSP and store them with a large LUT in my FPGA and another i2c master core in FPGA to send the stored i2c data to the 3 sen... 30 Jul 2010 11:51
Data-path accuracy in IIR filters?
I am working on a project where I need to implement 6-th order Butterworth low-pass filters in an FPGA. In some the bandwidth is low relative to the input data rate, whereas others have higher bandwidth. I can use ScopeIIR or Matlab to give me a good idea of coefficient accuracy for any given ratio of bandwidth t... 2 Aug 2010 18:02
SDRAM AutoPrecharge and Refresh
As a newbie I'm working on an SDR SDRAM controller in VHDL and looking at datasheet of the chip I read how to set CAS latency to 2. I'm just using only simple READA/WRITA (with autoprecharge) commands avoiding refresh/autorefresh ones. My answer is simple, Does "AutoPrecharged" commands (READA/WRITA) issue dr... 29 Jul 2010 18:28
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