FPGA
in [Hardware]
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Generic parameters in Actel Libero SmartDesign Components Hello I need some help for using Actel Libero IDE. The SmartDesign fonctionnality enable me to design my code as a block diagramm. This is a very convenient way to keep global view of my programm. But I don't know how to set generic parameters with components. I know this is really easy to do with Altera Active... 6 Aug 2010 18:10
A question from a VHDL beginner Dear everybody, I'm a beginner in using the VHDL and I'm experiencing some problems during the testing phase. I have developped a small VHDL model based on an Altera Cyclone FPGA and, using ModelSim, I have tested it in simulation mode. The results from simulation were goods, so I decided to synthesize the mode... 7 Aug 2010 11:28
Logic implementation probelm Hey i am using ise 9.1i for synthesizing my designs for spartan 3 fpgas. I am facing a very wierd problem. My system comprises of 1 xcs400 fpga and an ARM 7 processor. My RTL design is very modular. Here is the problem. I have a microcontroller interface in my rtl design to communicate with arm. other portions of ... 5 Aug 2010 10:12
Vendor Tool Stability A project I am considering undertaking would require that an FPGA's implementation flow (synthesis through bitgen) be routinely run in a scripted form at customer locations by the end customer, likely a non- engineer. The RTL input can be assumed to be good. All aspects of the vendor tools would be hidden from th... 6 Aug 2010 12:39
Xilinx ISE Webpack and Pipeline Optimization Here's a naive question, from a sometime FPGA user: A long time ago, a friend of mine who does _real_ digital design work was telling me how cool the (then new) Mentor tools were, because you could do a whole bunch of natural-looking combinational Verilog code in a module, then at the very end you could put in... 3 Aug 2010 19:07
Xilinx EasyPath Pricing Hi, i am working on a project where i am developing my architecture on Virtex-4 FPGA. My ultimate goal is to port my design to Xilinx EasyPath FPGA. But i dont have any idea, how xilinx charges for implementing design on EasyPath. there is no guide wither they charge against gate count, or FPGA family. what ever criter... 5 Aug 2010 10:12
PIT interrupt in Xilinx Hello, I am using Virtex 4 FPGA in ML 410 board and ISE 10.1. I want to use PIT interrupt and want to run a subroutine after every 1 second so as to print a statement. May I know how to use PIT interrupt along with code if possible? Regards --------------------------------------- Posted through... 3 Aug 2010 09:12
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Accelogic is looking for a Senior FPGA Engineer Hi all, See this post: http://jobview.monster.com/Senior-FPGA-Engineer-Job-Weston-FL-89641740.aspx Maybe someone here might be interested. The position seems both challenging and rewarding. Cheers, Jaime Aranguren ... 3 Aug 2010 07:02
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