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Download 100% Free Flash Templates/ files/ games
Download 100% Free Flash Templates/ files/ games Thx ... 19 May 2010 06:03
Building an Embedded Device? Tell VDC about your experiences for a chance to WIN!
VDC is conducting its annual survey of mobile and embedded engineers so if you are involved in the engineering of mobile or embedded systems/software, this is your chance to influence key solution suppliers. The research covers embedded software, hardware, tools, and development practices. Your thoughts will imp... 18 May 2010 13:38
Someting very stange happened since abou a week ago: I don´t receive any comp.arch.fpga messages. I can look at the online forum, but no email reaches me. I´m using googlegroups. I´m posting this just to see if I receive my own email, but if someone shares the same problem or have any idea, i´m listening. Daniel... 18 May 2010 12:32
MIG v3.0 inputs signal
Hi, I´m using MIG v3.0 to generate the VHDL code for a DDR SDRAM controller. I implement the design but I don´t know which is the format(values) the inputs signal, as for example app_af_addr, app_mask_data and app_wdf_data. And where do I declare the signals? Thanks a lot in advance. --------------... 31 May 2010 06:29
Basics on Xilinx Auroroa Core
Hi, I am about to design a packetizer logic to interface to Xilinx's Aurora Core. I will be using Virtex5 SX95. I have worked with Virtex2Pro MGTs before, but this is my first time working on Aurora and the GTX interfaces. And also this is my first time designing packetised/framed interfaces. I was reading the au... 18 May 2010 05:58
using ChipScope to debug external design
Hello, I am new to FPGA debugging using ChipScope. I know that ChipScope Pro tool is an internal logic analyser for FPGA Hardware designs.... But, is there a way to debug a hardware design that is not made on FPGA, using FPGA's ChipScope tool? Thanks for your help! Roger ---------------... 18 May 2010 02:44
Spartan 2 & 3, serial config and CS pin
Spartan 2 docs clearly says that, even though you are configuring the FPGA in serial mode, you should keep CS pin high. What about Spartan 3? I don't see something like: "Yes, Spartan 2 had an error, but it has been fixed in Spartan 3" ... 18 May 2010 15:52
Xilinx Synthesis Tool generates clock signals from combinatorial logic
Am 13.05.2010 16:18, schrieb John McCaskill: The problem is this bit of code: process (Inc_cnt, Dec_cnt) begin if Inc_cnt = '1' then Int_count <= Int_count + 1; elsif Dec_cnt = '1' then Int_count <= Int_count - 1; end if; end process; Inc_cnt looks like an a... 16 May 2010 02:43
Craignell1 FPGA DIL Module - No reserve on Ebay
We are selling off some our Craignell1 (original version) stock that we found in our recent move. One is on Ebay with no reserve. More will follow over the next few weeks or months. We have a small pile of these allocated to give away for deserving student or educational institution projects. Contact our sales te... 15 May 2010 11:30
Spartan 6 schedule
Hi, Is there any public information available about the roll-out schedule of production (non-ES) Spartan 6 devices, and their final price? Thanks, -- Sébastien Bourdeauducq The Milkymist project ... 19 May 2010 10:25
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