MIG v3.0 inputs signal
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From: Eagle_mk4 on 18 May 2010 07:51 Hi, I´m using MIG v3.0 to generate the VHDL code for a DDR SDRAM controller. I implement the design but I don´t know which is the format(values) the inputs signal, as for example app_af_addr, app_mask_data and app_wdf_data. And where do I declare the signals? Thanks a lot in advance. --------------------------------------- Posted through http://www.FPGARelated.com
From: lusch on 22 May 2010 09:06 On 18 Maj, 13:51, "Eagle_mk4" <eagle_mk4(a)n_o_s_p_a_m.hotmail.com> wrote: > Hi, I´m using MIG v3.0 to generate the VHDL code for a DDR SDRAM > controller. I implement the design but I don´t know which is the > format(values) the inputs signal, as for example app_af_addr, app_mask_data > and app_wdf_data. And where do I declare the signals? > > Thanks a lot in advance. > > --------------------------------------- > Posted throughhttp://www.FPGARelated.com I'd like to help you but you need to be more precies. lutex
From: Gabor on 22 May 2010 23:23 On May 18, 7:51 am, "Eagle_mk4" <eagle_mk4(a)n_o_s_p_a_m.hotmail.com> wrote: > Hi, I´m using MIG v3.0 to generate the VHDL code for a DDR SDRAM > controller. I implement the design but I don´t know which is the > format(values) the inputs signal, as for example app_af_addr, app_mask_data > and app_wdf_data. And where do I declare the signals? > > Thanks a lot in advance. > > --------------------------------------- > Posted throughhttp://www.FPGARelated.com In your MIG-generated directory structure should be a copy of the user guide that explains the use of these signals. For earlier versions of MIG this was ug086.pdf. As I recall it is not very clear about certain things like which address bits convert to row column and bank, but it has a few timing diagrams that help you understand the basics of the interface. for add_af_addr the lowest address bits map to the column address, the next bits up are the row address and the most significant bits are bank. If it hasn't changed since MIG 2.3, the address has a fixed width of 31 bits, so you need to add up your column/row/bank sizes to see how many of these 31 bits are really used. app_wdf_data is the write data input and is twice the width of the external DDR interface so it runs at the main clock rate rather than twice the rate. To determine how many words of data you need to provide with each write command, divide the burst length by two. Also remember to start a burst on a burst boundary. For example for a burst length of 4 you would provide two words of data and the low two bits of add_af_addr would be 00. app_mask_data is ignored if you don't generate the core with byte masking enabled. If you need to use it, each bit of the mask corresponds to one byte of app_wdf_data. A one bit in the mask "masks out" the associated byte. If you want to write all bytes it should be zero. Take a look at the interface description in the user guide to see the sequence for pushing commands and data into the core. HTH, Gabor
From: Eagle_mk4 on 25 May 2010 03:49 >On 18 Maj, 13:51, "Eagle_mk4" <eagle_mk4(a)n_o_s_p_a_m.hotmail.com> >wrote: >> Hi, I=B4m using MIG v3.0 to generate the VHDL code for a DDR SDRAM >> controller. I implement the design but I don=B4t know which is the >> format(values) the inputs signal, as for example app_af_addr, app_mask_da= >ta >> and app_wdf_data. And where do I declare the signals? >> >> Thanks a lot in advance. >> >> --------------------------------------- =A0 =A0 =A0 =A0 >> Posted throughhttp://www.FPGARelated.com > >I'd like to help you but you need to be more precies. > >lutex > I am using MIG v.3.0 for V4 XC4VLX160-FF1513 Development Kit of Avnet. I need to generate the vhdl code for a DDR SDRAM. With the MIG I generate the all vhdl code for the control signals, but the input signals aren´t generate and I don´t know how and where I declare it... Thanks and sorry for my bad English. --------------------------------------- Posted through http://www.FPGARelated.com
From: Eagle_mk4 on 25 May 2010 03:52
>On May 18, 7:51=A0am, "Eagle_mk4" <eagle_mk4(a)n_o_s_p_a_m.hotmail.com> >wrote: >> Hi, I=B4m using MIG v3.0 to generate the VHDL code for a DDR SDRAM >> controller. I implement the design but I don=B4t know which is the >> format(values) the inputs signal, as for example app_af_addr, app_mask_da= >ta >> and app_wdf_data. And where do I declare the signals? >> >> Thanks a lot in advance. >> >> --------------------------------------- =A0 =A0 =A0 =A0 >> Posted throughhttp://www.FPGARelated.com > >In your MIG-generated directory structure should be a copy >of the user guide that explains the use of these signals. For >earlier versions of MIG this was ug086.pdf. As I recall it is >not very clear about certain things like which address bits >convert to row column and bank, but it has a few timing >diagrams that help you understand the basics of the interface. > >for add_af_addr the lowest address bits map to the >column address, the next bits up are the row address >and the most significant bits are bank. If it hasn't changed >since MIG 2.3, the address has a fixed width of 31 bits, >so you need to add up your column/row/bank sizes to >see how many of these 31 bits are really used. > >app_wdf_data is the write data input and is twice the >width of the external DDR interface so it runs at the >main clock rate rather than twice the rate. To determine >how many words of data you need to provide with each >write command, divide the burst length by two. Also >remember to start a burst on a burst boundary. For >example for a burst length of 4 you would provide two >words of data and the low two bits of add_af_addr >would be 00. > >app_mask_data is ignored if you don't generate the core >with byte masking enabled. If you need to use it, each >bit of the mask corresponds to one byte of app_wdf_data. >A one bit in the mask "masks out" the associated byte. >If you want to write all bytes it should be zero. > >Take a look at the interface description in the user guide to >see the sequence for pushing commands and data into >the core. > >HTH, >Gabor > Thanks for your info, but I have to generate this signals in a new vhdl module or in the top level module?? Jose --------------------------------------- Posted through http://www.FPGARelated.com |