From: bonf on
>On 21 Apr., 18:15, Ed McGettigan <ed.mcgetti...(a)> wrote:
>> On Apr 20, 6:20=A0pm, "stephen.cra...(a)"
>> <stephen.cra...(a)> wrote:
>> > The CTO of Xilinx, during his keynote this morning at the
>> > Reconfigurable Architectures Workshop in Atlanta, made mention of the
>> > recent announcement of the Virtex 7 architecture. =A0My colleagues and
>> > assumed that either the announcement was very recent or not very well
>> > publicized as none of us had heard anything official regarding Virtex
>> > 7. A subsequent web search returned little except for a white paper
>> > 28nm technology.
>> > Does anyone know what announcement the CTO was referring to?
>> Either your colleagues misheard what was said our our CTO, Ivo Bolson,
>> mispoke. =A0There has been no announcement of a Virtex-7 FPGA family.
>> Xilinx did recently announce aspects of future families that will be
>> developed on the 28nm process
>> Ed McGettigan
>> --
>> Xilinx Inc.
>in Elektronik issue 8/2010 (bimonthly leading German electronics
>magazine) there's a featured article about "The FPGA of the Future".
>There is a statement that says :" The fabrication of [Xilinx's] 28nm
>devices will take place at Samsung and TSMC.
>The Spartan and Virtex product lines will be joined into a single
>product family for the 28 nm devices by Xilinx - PROBABLY named
>So, the name is in print already. It's NOT mentioned who came up with
>it, but unless Xilinx doesn't plan to name this new line totally
>different it's an obvious guess.
>Rumors travel fast. :-)
> Eilert

Just read the article. Nice article, but I think the joining of spartan and
virtex lines using a combined virtex 7 name is something that the author is
guessing, hence not a rumor.
Probably there a a number of grains of salt to the argument, and Xilinx has
indeed started to design virtex and spartan with the same design team.
Therefore it would make sense that the core logic of Virtex and Spartan
will converge in the Virtex 7 generation. But i do not believe that will
lead to a single line of FPGAs - there will always be the value (<$200,
spartan) and the performance (>$500, virtex) lines.
The interesting part of the article is that Altera is trying to develop a
28Gb/s transceiver for advanced optical interfaces (100Gb/s using 4 lines,
400Gb/s using 16 lines), which will push Xilinx to do the same. If this is
Virtex 7 or Virtex 8 remains to be seen, still waiting to see the ARM core
in Virtex 6 FX (or will it be pushed to Virtex 7?).

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