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From: smart0604 on 11 May 2010 14:57
I used the simple dual port ram in quartus with the altera fpga,but when i
simulate it in 100Mhz, the read data isn't what i haved writen in. but the
classic timing analyzer shows the fmax is about 200Mhz.could anybody help
me. I am so bothered with it.



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From: Nial Stewart on 12 May 2010 04:18
"smart0604" <smart0604(a)n_o_s_p_a_m.163.com> wrote in message
news:vPudndwfsuELNXTWnZ2dnUVZ_hCdnZ2d(a)giganews.com...
>I used the simple dual port ram in quartus with the altera fpga,but when i
> simulate it in 100Mhz, the read data isn't what i haved writen in. but the
> classic timing analyzer shows the fmax is about 200Mhz.could anybody help
> me. I am so bothered with it.


Are you using fully synchronous design?

Have you simulated the design to see what's happening?


The first is essential, the second is highly recommended!


Nial.


From: John_H on 12 May 2010 06:34
On May 11, 2:57 pm, "smart0604" <smart0604(a)n_o_s_p_a_m.163.com> wrote:
> I used the simple dual port ram in quartus with the altera fpga,but when i
> simulate it in 100Mhz, the read data isn't what i haved writen in. but the
> classic timing analyzer shows the fmax is about 200Mhz.could anybody help
> me. I am so bothered with it.
>
> ---------------------------------------        
> Posted throughhttp://www.FPGARelated.com

Do you expect the read data to show up the moment the read address is
valid? Or perhaps after the clock transition which samples the valid
read address?
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