Implementing bidirectional bus inside the FPGA [FPGA]

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From: Manmohan on 13 Apr 2010 19:43

Hi all,

I would like to implement a router mesh (3x3) with bidirectional links
within the FPGA . I am using a Virtex 4 board. Since there are a lot
of bidirectional buses in my design, I would like to know if it is
possible to implement all the buses using tristate logic? when I
snthesised only one single bidirectional bus, it was mapped to the
IOBs and consumed around 15% of the 240 IOBs.

I would like to know if there is any other way to implement a
bidirectional bus that does not use the IOBs ?

Thanks and Regards

Manmohan

From: Manmohan on 13 Apr 2010 19:49

On Apr 14, 7:43 am, Manmohan <mmm...(a)gmail.com> wrote:
> Hi all,
>
> I would like to implement a router mesh (3x3) with bidirectional links
> within the FPGA . I am using a Virtex 4 board. Since there are a lot
> of bidirectional buses in my design, I would like to know if it is
> possible to implement all the buses using tristate logic? when I
> snthesised only one single bidirectional bus, it was mapped to the
> IOBs and consumed around 15% of the 240 IOBs.
>
> I would like to know if there is any other way to implement a
> bidirectional bus that does not use the IOBs ?
>
> Thanks and Regards
>
> Manmohan

-----------------------------------------

I would like to add that my buses do not have to interface externally
to the chip. (ie none of the bidirectional links will have to go out
of the FPGA ) everything remains inside. So is there any way to
implement the same. ???

From: Andy Peters on 13 Apr 2010 19:50

On Apr 13, 4:43 pm, Manmohan <mmm...(a)gmail.com> wrote:
> Hi all,
>
> I would like to implement a router mesh (3x3) with bidirectional links
> within the FPGA . I am using a Virtex 4 board. Since there are a lot
> of bidirectional buses in my design, I would like to know if it is
> possible to implement all the buses using tristate logic? when I
> snthesised only one single bidirectional bus, it was mapped to the
> IOBs and consumed around 15% of the 240 IOBs.
>
> I would like to know if there is any other way to implement a
> bidirectional bus that does not use the IOBs ?

No, internal tristates have vanished from Brand X FPGAs after the
XC4000 series.

I don't miss them. I don't see how they can possibly have any
advantage over distinct "going this way" and "going that way" buses.

-a

From: Manmohan on 14 Apr 2010 04:24

From: Manmohan on 14 Apr 2010 04:45

On Apr 14, 7:50 am, Andy Peters <goo...(a)latke.net> wrote:
> On Apr 13, 4:43 pm, Manmohan <mmm...(a)gmail.com> wrote:
>
> > Hi all,
>
> > I would like to implement a router mesh (3x3) with bidirectional links
> > within the FPGA . I am using a Virtex 4 board. Since there are a lot
> > of bidirectional buses in my design, I would like to know if it is
> > possible to implement all the buses using tristate logic? when I
> > snthesised only one single bidirectional bus, it was mapped to the
> > IOBs and consumed around 15% of the 240 IOBs.
>
> > I would like to know if there is any other way to implement a
> > bidirectional bus that does not use the IOBs ?
>
> No, internal tristates have vanished from Brand X FPGAs after the
> XC4000 series.
>
> I don't miss them. I don't see how they can possibly have any
> advantage over distinct "going this way" and "going that way" buses.
>
> -a

Hi Below is the code I used for implementing a bidirectional
transciever...
IENTITY bidir IS
PORT(
bidir : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0);
oe, clk : IN STD_LOGIC;
inp : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
outp : OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
END bidir;

ARCHITECTURE Behav OF bidir IS
SIGNAL a : STD_LOGIC_VECTOR (7 DOWNTO 0); -- DFF that stores
-- value from input.
SIGNAL b : STD_LOGIC_VECTOR (7 DOWNTO 0); -- DFF that stores
BEGIN -- feedback value.

bidir <=a when oe = '1' else (others => 'Z');
PROCESS(clk)
BEGIN
IF clk = '1' AND clk'EVENT THEN -- Creates the flipflops
a <= inp;
b <= bidir;
outp <= b;
END IF;
END PROCESS;

I also instantiated the above component as shown below in a top level
module :

entity Top is
Port ( inp1 : in STD_LOGIC_VECTOR (7 downto 0);
inp2 : in STD_LOGIC_VECTOR (7 downto 0);
out1 : out STD_LOGIC_VECTOR (7 downto 0);
out2 : out STD_LOGIC_VECTOR (7 downto 0);
oe1,oe2,clk: in STD_LOGIC
);
end Top;
architecture Behavioral of Top is

component bidir is

port ( bidir : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0);
oe, clk : IN STD_LOGIC;
inp : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
outp : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
end component;

signal data : STD_LOGIC_VECTOR ( 7 downto 0);

begin

t1 : bidir port map( inp => inp1, outp => out1, oe => oe1, clk =>
clk, bidir => data);
t2 : bidir port map(inp => inp2, outp => out2, oe => oe2, clk => clk,
bidir => data);

end Behavioral;

I synthesized the entire design using Xilinx IST : The synthesise
mapped the tristate logic to IOBs and this single design was taking
nearly 15 % of all available IOB.

Then I changed the options in Xilinx IST and unselected the Add IO
Buffers option in the synthesis options. When I did that... I got the
following synthesis message :

WARNING:Xst:2042 - Unit bidir: 8 internal tristates are replaced by
logic (pull-up yes): bidir<0>, bidir<1>, bidir<2>, bidir<3>, bidir<4>,
bidir<5>, bidir<6>, bidir<7>.
INFO:Xst:2261 - The FF/Latch <t2/b_0> in Unit <Top> is equivalent to
the following FF/Latch, which will be removed : <t1/b_0>
INFO:Xst:2261 - The FF/Latch <t2/b_1> in Unit <Top> is equivalent to
the following FF/Latch, which will be removed : <t1/b_1>
INFO:Xst:2261 - The FF/Latch <t2/b_2> in Unit <Top> is equivalent to
the following FF/Latch, which will be removed : <t1/b_2>
INFO:Xst:2261 - The FF/Latch <t2/b_3> in Unit <Top> is equivalent to
the following FF/Latch, which will be removed : <t1/b_3>
INFO:Xst:2261 - The FF/Latch <t2/b_4> in Unit <Top> is equivalent to
the following FF/Latch, which will be removed : <t1/b_4>
INFO:Xst:2261 - The FF/Latch <t2/b_5> in Unit <Top> is equivalent to
the following FF/Latch, which will be removed : <t1/b_5>
INFO:Xst:2261 - The FF/Latch <t2/b_6> in Unit <Top> is equivalent to
the following FF/Latch, which will be removed : <t1/b_6>
INFO:Xst:2261 - The FF/Latch <t2/b_7> in Unit <Top> is equivalent to
the following FF/Latch, which will be removed : <t1/b_7>
INFO:Xst:2261 - The FF/Latch <t2/outp_0> in Unit <Top> is equivalent
to the following FF/Latch, which will be removed : <t1/outp_0>
INFO:Xst:2261 - The FF/Latch <t2/outp_1> in Unit <Top> is equivalent
to the following FF/Latch, which will be removed : <t1/outp_1>
INFO:Xst:2261 - The FF/Latch <t2/outp_2> in Unit <Top> is equivalent
to the following FF/Latch, which will be removed : <t1/outp_2>
INFO:Xst:2261 - The FF/Latch <t2/outp_3> in Unit <Top> is equivalent
to the following FF/Latch, which will be removed : <t1/outp_3>
INFO:Xst:2261 - The FF/Latch <t2/outp_4> in Unit <Top> is equivalent
to the following FF/Latch, which will be removed : <t1/outp_4>
INFO:Xst:2261 - The FF/Latch <t2/outp_5> in Unit <Top> is equivalent
to the following FF/Latch, which will be removed : <t1/outp_5>
INFO:Xst:2261 - The FF/Latch <t2/outp_6> in Unit <Top> is equivalent
to the following FF/Latch, which will be removed : <t1/outp_6>
INFO:Xst:2261 - The FF/Latch <t2/outp_7> in Unit <Top> is equivalent
to the following FF/Latch, which will be removed : <t1/outp_7>

Could you please help me understand what is happening?

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