Prev: Read from the compact flash
Next: Clock Mux by software ...
From: Symon on 14 Apr 2010 08:08
On 4/14/2010 12:43 AM, Manmohan wrote:
>
> I would like to know if there is any other way to implement a
> bidirectional bus that does not use the IOBs ?
>
>
> Thanks and Regards
>
> Manmohan

Virtex 4 doesn't have internal tri-stated signals. Do it another way.

HTH, Syms.
From: Gabor on 14 Apr 2010 09:05
On Apr 14, 7:33 am, glen herrmannsfeldt <g...(a)ugcs.caltech.edu> wrote:
> Manmohan <mmm...(a)gmail.com> wrote:
>
> (snip)
>
> > So does this mean that it is possible to have bidirectional buses
> > inside the FPGA without using the tristate logic from the IOBs?
>
> The IOBs would only work if the bus was external.
>
> You can design with internal tristate, as far as I know,
> with most tools, but the implementation is more like a MUX
> going into one bus, and then to all inputs driven by the bus.
>
> If I did it, it would be AND gates with one input for the
> signal and the other for the enable.  Then OR all the AND gate
> outputs together, and send that to all inputs reading from the bus.
>
> I don't know if that is how it is implemented, but it could
> be done that way.  You can also do it yourself.
>
> -- glen

Actually the AND / OR approach is used in the processor
buses for both MicroBlaze and Power PC. i.e. the enable
line AND's with the data so un "driven" lines are zero
and the sources are all ORed together. If you code tristate
buses and allow XST to translate them into LUT's, you'll
more likely end up with MUXes.

By the way, internal tristates were still available through
the original Virtex series (Virtex and Virtex E) and Spartan
2. However, as others mentioned, internal tristates are
gone from newer devices.

Regards,
Gabor
From: Symon on 14 Apr 2010 10:05
On 4/14/2010 1:08 PM, Symon wrote:
> On 4/14/2010 12:43 AM, Manmohan wrote:
>>
>> I would like to know if there is any other way to implement a
>> bidirectional bus that does not use the IOBs ?
>>
>>
>> Thanks and Regards
>>
>> Manmohan
>
> Virtex 4 doesn't have internal tri-stated signals. Do it another way.
>
> HTH, Syms.

http://groups.google.com/group/comp.arch.fpga/msg/d520d67ab735e3cc?hl=en
From: dalai lamah on 14 Apr 2010 14:10
Un bel giorno Andy Peters digit�:

> No, internal tristates have vanished from Brand X FPGAs after the
> XC4000 series.

Actually I routinely use the resolved signals (i.e. std_logic_vector with
'1', '0' and 'Z' states) for internal shared buses, and they work fine for
every FPGA I've tried. Am I doing it wrong?

--
emboliaschizoide.splinder.com
From: Rob Gaddi on 14 Apr 2010 14:24
On 4/14/2010 11:10 AM, dalai lamah wrote:
> Un bel giorno Andy Peters digit�:
>
>> No, internal tristates have vanished from Brand X FPGAs after the
>> XC4000 series.
>
> Actually I routinely use the resolved signals (i.e. std_logic_vector with
> '1', '0' and 'Z' states) for internal shared buses, and they work fine for
> every FPGA I've tried. Am I doing it wrong?
>

You routinely write code _asking_ for resolved signals. What you get is
the synthesizer turning them into unidirectional logic with a large
number of ands, ors, and muxes. The hardware itself physically cannot
support tristate buses.

--
Rob Gaddi, Highland Technology
Email address is currently out of order
First  |  Prev  |  Next  |  Last
Pages: 1 2 3 4 5
Prev: Read from the compact flash
Next: Clock Mux by software ...