From: daver2 on 18 Apr 2010 13:45
This problem has been driving me batty now for a while. I have spent
ages tracking down a bug in my VHDL only to find there is no bug at
all - just that the initialisation data I have pre-set into a VIRTEX-4
BRAM does not appear to be there after the FPGA has been loaded. I
have tried a number of different experiments - and finally stripped
the logic back to a clock circuit, a few switches and LED's and a
single BRAM instance with the same problem...
I am using a HydraXC-30 module with a Xilinx VIRTEX-4 FPGA. I am using
Xilinx WebPACK version 11.1 to configure the device. I am then
transferring the bit image onto an SD card and booting the FPGA from
there - as is normal with the HydraXC-30.
Even though I have instantiated a BRAM with the INIT_XX attributes set
- the BRAM always seems to boot up without the initialisation data
present. The RAM does (however) behave correctly (i.e. I can write
data into a memory cell and I can read the same data back out of it
again at some point in the future).
I have used the FPGA editor and I can open the instance of the BRAM
and see the init data within the window OK.
I have even dumped out the bit file as ASCII, changed a byte in my
initialisation attributes and dumped the bit file again. I can see
differences within the two bit files indicating that the WebPACK tools
have stored my data into the bitstream. I have also tried rebuilding
the bit file without making any changes to the initialisation
attributes and the only thing that changes in the bit file is the
header right at the front of the bit file (date and time of build) -
just to make sure I am not confusing myself.
Has anyone else come across this problem?
Are there any build options or configuration options that could
disable loading the BRAM initialisation data into the FPGA?
WebPACK is using the default stepping for the VIRTEX-4 (1) but the
FPGA itself maybe stepping 2 (part number XC4VLX25 SF363CNQ0533
DD16169A 10C). Changing the stepping within WebPACK causes it to
change my clock DCM to "auto calibration" mode and my clock circuit
refuses to work after that! I haven't looked into this problem further
- but I was under the impression that stepping levels should be
upwardly compatable (i.e. code generated for stepping 1 should work on
Any help gratefully received,
From: jt_eaton on 18 Apr 2010 18:26
>Even though I have instantiated a BRAM with the INIT_XX attributes set
>- the BRAM always seems to boot up without the initialisation data
>present. The RAM does (however) behave correctly (i.e. I can write
>data into a memory cell and I can read the same data back out of it
>again at some point in the future).
>Any help gratefully received,
Make sure your init file size EXACTLY matches your declared ram size. If
it's off either way you get no init and a warning message in the log file
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