From: sandeep on


Hello Friends



Our group has finished a project which has
different modules in it, executing different tasks. We need to call
this different modules of the project from a different main file. For
callling each module, I have set a single bit input port for each
module in the project so that when these input ports are set, the
modules start working.



According to my knowledge in verilog, we could call the entire project
or all the modules together by setting all the input ports. But what
we want is,calling different modules of the project at different times
or calling one module more than once and other modules only once.(I
hope you understand this).I have tried to set the input ports
sequentially but only the last call or the last call of the module is
onlly executed.All the before calls are not getting executed.



Here are my some modules in the project



module project:



case(state)

IDLE: begin

if(reset == 1) begin

-----

--------

-------

next_state = STATE0;

end



STATE0: begin

if(inititate_i == 1) begin

---------

---------

---------

next_state = STATE1;

end

else

next_state = IDLE;

end



endmodule



My main program from which I called my project is -



mainprogramme:



main project instance;



main project reset =1;

main project inititate_i = 1;

main project reset = 1;

endmainprogramme



In the above case, only my second call of the reset is being
executed(I have written code in my project which will retain my old
values of the register,so there is no worry of that may be the values
are getting overwriiten). There is a simple way of calling the
different modules in the main project by just using a counter and
running t he module as many times as i require. But we don't want
that, beacuse the number of times a single module is called is not
decided before.



Could any one please give me suggestions for solving this probelm.I
would be great ful for the help.



Please help me. I have been trying on this problem from many days but
with no success.



From: Ed McGettigan on
On Jun 5, 12:31 am, sandeep <sssgsand...(a)gmail.com> wrote:
> Hello Friends
>
>                        Our group has finished a project which has
> different modules in it, executing different tasks. We need to call
> this different modules of the project from a different main file. For
> callling each module, I have set a single bit input port for each
> module in the project so that when these input ports are set, the
> modules start working.
>
> According to my knowledge in verilog, we could call the entire project
> or all the modules together by setting all the input ports. But what
> we want is,calling different modules of the project at different times
> or calling one module more than once and other modules only once.(I
> hope you understand this).I have tried to set the input ports
> sequentially but only the last call or the last call of the module is
> onlly executed.All the before calls are not getting executed.
>
> Here are my some modules in the project
>
> module project:
>
> case(state)
>
> IDLE: begin
>
> if(reset == 1) begin
>
> -----
>
> --------
>
> -------
>
> next_state = STATE0;
>
> end
>
> STATE0: begin
>
> if(inititate_i == 1) begin
>
> ---------
>
> ---------
>
> ---------
>
> next_state = STATE1;
>
> end
>
> else
>
> next_state = IDLE;
>
> end
>
> endmodule
>
> My main program from which I called my project is -
>
> mainprogramme:
>
> main project instance;
>
> main project reset =1;
>
> main project inititate_i = 1;
>
> main project reset = 1;
>
> endmainprogramme
>
> In the above case, only my second call of the reset is being
> executed(I have written code in my project which will retain my old
> values of the register,so there is no worry of that may be the values
> are getting overwriiten). There is a simple way of calling the
> different modules in the main project by just using a counter and
> running t he module as many times as i require. But we don't want
> that, beacuse the number of times a single module is called is not
> decided before.
>
> Could any one please give me suggestions for solving this probelm.I
> would be great ful for the help.
>
> Please help me. I have been trying on this problem from many days but
> with no success.

It appears that you are trying to apply software design conventions to
a hardware design and it really doesn't make sense.

You are designing for an FPGA and the hardware logic that you are
describing is always present and always running in parallel. Hardware
logic modules are not "called" as you would with a software sub-
routine they are instantiated and always present.

Ed McGettigan
--
Xilinx Inc.