Spartan3a: improving DCM performance and "To achieve optimalfrequency synthesis performance..." warning
in [FPGA]
|
Prev: Best clock output pin in Spartan-3
Next: Spartan3a: improving DCM performance and "To achieve optimal frequency synthesis performance..." warning
From: Philip Pemberton on 10 Aug 2010 21:43 Hi guys, Can anyone explain the following INFO alert I saw in my ISE build log? INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis performance with the CLKFX and CLKFX180 outputs of the DCM comp clock_generator/DCM_SP_INST, consult the device Interactive Data Sheet. This is on a Spartan3a design which uses a DCM to multiply the incoming 25MHz clock up to 50MHz, then feeds it to another DCM which generates CLK0 and CLK90 (0 and 90 degree phase-shifted clocks) from the 50MHz clock. The 0deg clock is used to drive the CPU, SDRAM controller and other stuff, while the 90deg clock is used to drive the SDRAM itself. I've tried searching Xilinx's website for an "interactive datasheet" and found nothing. This INFO alert caught my interest because I'd like to get my design running a bit faster (66MHz would be nice, 75MHz or 100MHz even better, the SDRAM tops out at 133MHz). In theory a single-DCM design should be good to 133MHz (at least that's what the timing report says), but as soon as I add the frequency synth, the max frequency drops to 60MHz or so. Is there anything I can do to eek a bit more speed out of this thing? Thanks, -- Phil. usenet10(a)philpem.me.uk http://www.philpem.me.uk/ If mail bounces, replace "10" with the last two digits of the current year |