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From: Frank van Eijkelenburg on 11 Aug 2010 11:50
On Jul 6, 12:12 pm, Michael S <already5cho...(a)yahoo.com> wrote:
> On Jul 6, 11:00 am, Frank van Eijkelenburg
> <fei.technolut...(a)gmail.com> wrote:
> > I hope to fix the problem before my vacation (only one day left :)
> Something, I most certainly DO NOT RECOMMEND for final solution, but
> it could help to go to vacation in better mood.
> Scrap all the schoolbook nice&complex WindowsDMAAPI stuff. Instead,
> take your Irp->MdlAddress, do MmGetMdlPfnArray() and access physical
> addresses directly. It's wrong, it's immoral but on simple x86/x64 PC
> or on small dual-processor server it always work.
> Just don't forget to bring back the officialDMAAPI when you are back
> from vocation and have more time than a few hours.
Finally, I solved the problem. For those who want to learn from
mistakes of others, here comes the cause of the problem:
The packets which were transmitted to the pc were too large (more than
the maximum payload size of the receiver). In that case, the packets
are simply dropped (no errors). Of course I have to read the maximum
payload size from the device control register in the PCI Express
From: Michael S on 11 Aug 2010 18:40
On Aug 11, 5:50 pm, Frank van Eijkelenburg
> Finally, I solved the problem. For those who want to learn from
> mistakes of others, here comes the cause of the problem:
> The packets which were transmitted to the pc were too large (more than
> the maximum payload size of the receiver). In that case, the packets
> are simply dropped (no errors). Of course I have to read the maximum
> payload size from the device control register in the PCI Express
> Capability structure.
> best regards,
Thanks for the interesting update, Frank. I never even thought in that
Last time we did PCIe on FPGA we used Altera core with Avalon-MM
wrapper. This configuration doesn't support outstanding packets that
are longer than 256 bytes so, obviously, we were immune to maximum
payload size trap.
From: FPGA on 12 Aug 2010 14:42
On Jul 1, 11:03 am, Frank van Eijkelenburg
> I have a custom made PCIe board with a Virtex 5 FPGA on which I
> implemented a DMA unit which uses the PCIe endpoint block plus v1.14.
> I also implemented simple read/write operations from the PC to the
> board (the board responds with completion TLPs). The read/write
> operations are working, DMA is not working
> The board is inserted in a pc with Windows 7 64 bits platform. An
> application allocates virtual memory and passes the memory block to
> the driver. The driver locks the memory and converts the virtual
> addresses into physical addresses. These physical addresses are
> written to the FPGA.
> When I start an DMA operation, I can see in chipscope the correct
> physical addresses in the TLP header. However, I do not see the
> correct values in the allocated memory. What can I do to check where
> it is going wrong?
> Another question is about the memory request TLPs. What should I use,
> 32 or 64 bit write requests? Or do I have to check runtime if the
> physical memory address is below or above the 4 GB (and use
> respectively 32 and 64 bit requests)?
> Thanks in advance,
Could somebody please help me to identify as to what the "4177" suffix
calls out on this specific Xilinx Virtex-5 device and if it is
compatible to the same device without this suffix.
XC5VTX240T-2FF1759I4177 vs. XC5VTX240T-2FF1759I . Avnet list them both
on their website but the with the "4177" suffix the price is roughly
$1,000.00 more?. It doesnt seem like it would be a specific customer
code as they advertize both to the public? Any help with this is