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From: Peter Ryser on 12 Oct 2006 10:27
Sylvain is right. In Virtex-4 the user can control CCLK and the Done pin
through the STARTUP block. This feature was added in combination with
the USR_ACCESS_VIRTEX4 port.

The combination allows for uniform access to data appended to the
configuration bitstream in all configuration modes (master/slave
serial/selectmap and JTAG). Independent of the configuration mode the
data will always show up the exact same way which makes it much easier
for a user to use.

XAPP719 explains how that feature can be used to configure the PPC
caches from a Platform Flash. However, that's only one possible use
case. Other use case do not involve the PPC but are for loading
persistent user data.

- Peter

Sylvain Munaut <SomeOne(a)SomeDomain.com> wrote:
> Hi
>
>
>>Virtex-4 has many new things, one of them is access to CCLK as output
>>after configuration. CCLK control is required to readback data from XCF
>>devices, this approuch is described in Xilinx Application note XAPP482.
>>Until today I did live in believe that this was the reason why startup
>>primitive was modified in Virtex-4, but today I was about to check the
>>pinout for XCF data read able design, and uuuuups - CCLK access is
>>added in Virtex-4 but at the same time input access to DIN has been
>>removed!? Or at least I cant see how to read the DIN pin from FPGA
>>fabric. So if for Spartan-3 the XAPP482 solution suggested a FPGA I/O
>>pin to be routed parallel to CCLK, then well this wire is not required
>>in Virtex-4, but now we need another FPGA I/O to be routed to DIN
>>because DIN is no longer accessible?
>>
>>I cant belive this to be true ! But I also fail to see any other
>>solution for XCF data read with Virtex-4. Of course a solution would be
>>using Virtex-5 where the DIN is again made accessible with the modified
>>again STARTUP primitive.
>>
>>I am too glad that I did not trust me belives that the CCLK fix in the
>>Virtex-4 fixed the additional wiring requirement as per XAPP482 and
>>checked the design before submitting to PCB fabrication.
>>
>>I wish Xilinx would update XAPP482 with wiring diagram for all
>>families. The DIN no access thing was really an almost unbelivable
>>surprise for me :(
>
>
> Isn't this what the USE_ACCESS_VIRTEX4 is for ?
>
> Sylvain
>
From: Antti on 12 Oct 2006 11:42
Peter Ryser schrieb:

> Sylvain is right. In Virtex-4 the user can control CCLK and the Done pin
> through the STARTUP block. This feature was added in combination with
> the USR_ACCESS_VIRTEX4 port.
>
> The combination allows for uniform access to data appended to the
> configuration bitstream in all configuration modes (master/slave
> serial/selectmap and JTAG). Independent of the configuration mode the
> data will always show up the exact same way which makes it much easier
> for a user to use.
>
> XAPP719 explains how that feature can be used to configure the PPC
> caches from a Platform Flash. However, that's only one possible use
> case. Other use case do not involve the PPC but are for loading
> persistent user data.
>
> - Peter
>
Dear Peter,

I know very well that
1) STARTUP provides access to CCLK and DONE
2) USR_ACCESS can be used for many nice thing

however if it is required to read the DIN from the FPGA
fabric then it doesnt help ASFAIK ?

I could get pieces of data from external memory if
it is specially prepared, i know.

but in my case i really need the DIN as it available
in ALL OTHER Xilinx FPGA's ***EXCEPT*** Virtex-4

the configuration is provided in master serial mode
from external SPI flash, the Flash DO goes to FPGA DIN
SCK to CCLK

everything would be fine, but in virtex-4 the DIN is no
longer accessible or is there some trick ??

Antti

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