BRAM with output register using ram_style attribute
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From: John_H on 26 May 2010 06:22 On May 25, 7:47 pm, "shantesh" <shantesh84(a)n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote: > Hello, > > I'm curious to know if there is a way we could tell the synthesizer to use > registered mode of BRAM when using ram_style "block" attribute. > > The registered mode otherwise can be enabled by instantiating a BRAM with > DOA_REG, DOB_REG set to 1 and REGCEA, REGCEB set to '1'. > > For example, the VHDLcode below infers a BRAM. However, it does not enable > the registered mode. To get around with it, I've added a process which > registers the output wherever this memory is instantiated. This added > register occupies a slice. Is there a way I can tell the synthesizer to use > the register inside of BRAM (that way I could save resources). > > ==== > attribute ram_style : string; > attribute ram_style of RAM : signal is "block"; > > begin > > process (clk) > begin > if clk'event and clk = '1' then > if en = '1' then > if we = '1' then > RAM(conv_integer(addr)) <= di; > end if; > do <= RAM(conv_integer(addr)); > end if; > end if; > end process; > > end; > ===== > > Thanks, > Shantesh > > --------------------------------------- > Posted throughhttp://www.FPGARelated.com Rather than adding a process, have you tried simply adding a register stage in the process where the RAM is inferred? Somethimes synthesizers understand your intentions better when they're all together.
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