C++: 64 bit performance vs. 32 bit
|
From: Andy Freeman on 14 Feb 2006 14:32 Andy Glew wrote: > I have said, in this forum, for nigh on years now: eventually we must > go to multilevel register files. A small L1 register file that has > lots of ports. A large L2 register file that has fewer ports. Hell, > it could even be in main memory. Fair enough. > If you want to add more architectural registers, add them to the L2 > PRF. Why should the register file hierarchy be architecturally visible? -andy
From: Andy Glew on 14 Feb 2006 16:10 anton(a)mips.complang.tuwien.ac.at (Anton Ertl) writes: > Andy Glew <first.last(a)employer.domain> writes: > >With x86-64 roughly 64 architectural registers > > How do you compute that? I compute: > > 16 GPRs > 16 xmm > 8 387/mmx > -- > 40 I say roughly, because both AMD and Intel have extra microcode temporary registers - which live in the RRF, if you have one, but which are not visible to external software. I say roughly because exactly how many temps and other extra stuff you have depends on your microarchitecture.
From: Brian Hurt on 14 Feb 2006 16:33 Andy Glew <first.last(a)employer.domain> writes: >Bernd Paysan <bernd.paysan(a)gmx.de> writes: >Consider a Willammette/Psc/K8 era machine. >With x86-64 roughly 64 architectural registers (exactly how many depends). How are you getting 64? I get 32- 16 integer, and 16 FP/SSE. And that's *after* the doubling. It used to be 16 registers (8 int, 8 FP/SSE). Also note that the increased number of architectural registers means less false sharing of registers, and thus less need for rename registers. >It's ironic: we might well have better performance - larger >instruction windows - if we had fewer architectural registers. This is probably true for the Itanium. It is demonstratably false for the x86. It probably isn't worth the effort to try and get the x86 to 32 registers each of int/float. But it was certainly worth it to go to 16 each. Brian
From: Anton Ertl on 14 Feb 2006 17:05 Andy Glew <first.last(a)employer.domain> writes: >anton(a)mips.complang.tuwien.ac.at (Anton Ertl) writes: > >> Andy Glew <first.last(a)employer.domain> writes: >> >With x86-64 roughly 64 architectural registers .... >I say roughly, because both AMD and Intel have extra microcode >temporary registers - which live in the RRF, if you have one, but >which are not visible to external software. > >I say roughly because exactly how many temps and other extra stuff you >have depends on your microarchitecture. I guess that you meant something other than "architectural registers", then. - anton -- M. Anton Ertl Some things have to be seen to be believed anton(a)mips.complang.tuwien.ac.at Most things have to be believed to be seen http://www.complang.tuwien.ac.at/anton/home.html
From: Andy Glew on 14 Feb 2006 17:33
> > If you want to add more architectural registers, add them to the L2 > > PRF. > > Why should the register file hierarchy be architecturally visible? It should not be. From the users' point of view, there should be just "N" registers of different types. The user should not care about microarchitecture. I'm just trying to say that adding more architectural registers should not be done unless there is microarchitectural work done to make them usable. That microarchitectural work might include * multilevel register files * backing off multithreading * reducing superscalarness * reducing RF ports some other way (e.g. the way P6 did) or even * magic circuit tricks |