From: rickman on
On Feb 6, 9:34 am, Uwe Bonnes <b...(a)elektron.ikp.physik.tu-> wrote:
> my original question was about constraining
> minimum hold times. I still don't see a way to do so.

Sorry, I thought that was explained. I can't say categorically, but I
don't think there is a way. Bsides, your approach of using a global
clock input and a register in the IOB means the delay is not
controllable by layout. It is what the data sheet says it is and they
typically don't spec minimum delays.

Inside the chip there is no reason to use minimum delays if you are
using the clock routing resources. Any other clock routing is at your
own risk and I have never seen tools to support that.