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From: Tim Wescott on 14 Jun 2010 11:40
On 06/13/2010 09:30 PM, crasic wrote:
>> "Or let the DPLL run as open loop"
>>
>> Do you mean if you feed a constant to your NCO, whatever that may be?
>> If that's the case, then your problem is your reference clock. This is
>> backed up by your results with that Stanford Research Systems function
>> generator -- your DPLL will see it's reference clock as "truth" even if
>> it's jittery. Give it a jittery reference clock and feed it the World's
>> Cleanest Signal as input and it'll see jitter in that input and "clean"
>> it right up.
>
>> Tim Wescott
>> Control system and signal processing consulting
>> www.wescottdesign.com
>>
>
>
> This DPLL design runs at a frequency set at with an output divider, it is
> essentially a pulse-steal design that adds or subtracts fast clock pulses
> to the base frequency. The capture range for a 100MHz clock is
> approximately 0.1f_set so with the center frequency of ~700Khz we get a
> 8Khz bandpass.
>
> If the signal is outside the lockrange or there is no signal applied the
> pll runs at its open loop frequency set by the divider.
>
>
>
>
>> To begin with: FPGA doesn't mate with low jitter. No matter what
>> filtering is, you can expect jitter in ~100ps range, due to coupling on
>> the crystal. This is rather poor performance. If you need better then
>> that, do a specialized analog circuit.
>>
>> Vladimir Vassilevsky
>> DSP and Mixed Signal Design Consultant
>> http://www.abvolt.com
>
>
> The end design will have some additional digital circuitry on the board in
> the form of an ADC and control circuitry so if there are any digital
> non-fpga solutions that could supplement our fpga filter I'm open to it. We
> are trying to replace specialized (power hungry and expensive as well!)
> analog circuitry with a digital solution so going back to it would be
> pretty redundant!

I'll reiterate my suggestion to post the question on
sci.electronics.design -- mentioning your center frequency, jitter
requirements, and power consumption needs will get you more response.
Spin it not as "why won't my FPGA work" but as "what approach should I
take", possibly mentioning what you've just learned about the FPGA approach.

There's some smart folks over there, and many of the ones who can help
you don't frequent this group.

> Could we potentially expect better performance with a programmable logic
> chip instead of an FPGA?

Field Programmable Gate Array -- what's not programmable logic about
that? You mean PAL?

I suspect that the route to take doing this in digital logic is to
isolate the logic that's actually doing the digital processing of the
clock, and do _just_ that action with it. If you can control it from an
FPGA through suitably isolated signals well and good. If the problem
with the FPGA is all the signals everywhere on the chip coupling into
each other a little bit, making thresholds noisy, then replacing all
that with 74AC logic or whatever is fast enough (can you even get ECL
any more?) and keeping it _quiet_ would probably help.

> The clock source is a generic crystal generator. Unfortunately I didn't
> have the chance to measure the clock jitter and measuring it now through
> the fpga results in some crazy readings (~1hz at 50 Mhz, or 100 times worse
> than our pll output jitter)

Every high-precision problem that I've ever worked on has been like
peeling an onion. Any time you're trying to measure or control things
in the parts-per-million your effort becomes a lot like peeling an onion
-- you tear a layer off, you cry a lot, and you find that the problem is
a little smaller. Then you recover your composure and you do it again.

Don't expect this to be any different...

--
Tim Wescott
Control system and signal processing consulting
www.wescottdesign.com
From: j on 14 Jun 2010 13:34
Pll’s incorporate some fundamental blocks:

PD, filter, vco/nco and a feedback componet usually a divider
function. The implementation can be either digital or analog …
stability analysis is fundamentally the same.

The overall loop function is that of a bp about the carrier of the
output vco/nco.

Two applications of the pll are: 1) track a noisy ref with good long
term stability but terrible short term stability, i.e., gps 1 pulse/
sec clock and generate a higher frequency system clock with good short
and long term stability. 2) use a good ref with great phase noise
characteristics to generate a multiplied up frequency with worse phase
noise performance, ( how much worse is the art of synthesizer design).

The point is that in side the loop bw, the Pll acts as a phase noise
multiplier. The phase noise profile of the vco/nco will determine the
jitter characteristics of the system.

In this case it sounds like the op is trying to use the Pll to derive
short term stability at what frequency output isn’t clear to me.

My personal experience with Pll’s inside of FPGA’s or ASIC’s is that
it takes careful planning to get good phase noise performance, i.e.,
jitter performance will suffer. The coupling of correlated and non-
correlated signals are horrendous. Just trying to figure out how to
probe the output vco and get believable results can be a task.
Obviously the definition of “good” needs to be defined up front, i.e.,
“what is the desired phase noise profile”.

My suggestions would be to measure the phase noise profile of the ref
and compare that to the phase noise profile of the output vco/nco and
determine if the output is justified by the loop parameters. If the
phase noise profile, jitter, of the output vco/nco running open loop
is worse than the ref profile by definition you won’t be able to make
the system better.

jdc
From: glen herrmannsfeldt on 14 Jun 2010 15:21
Vladimir Vassilevsky <nospam(a)nowhere.com> wrote:
(snip)

> Thanks for the link. Interesting reading; although in the real world
> they rarely give out *any* jitter specs for digital parts. Yes, jitter
> is crucial in Class D; and this is one of the reasons why naive digital
> amplifiers have mediocre performance. Other area where it matters is the
> RF signal generation.

This reminds me of the stories 30 years ago that Class D audio
amplifiers at higher powers would become popular and affordable
in a short number of years. Now, 30 years later, I hear even
less about them. Now that we have much better high-power
transistors, presumably better for both analog and digital
designs, why is it that Class D never caught on.

(Especially with the "digital is always better" mindset
that so many have now.)

-- glen
From: crasic on 15 Jun 2010 00:54
>I'll reiterate my suggestion to post the question on
>sci.electronics.design -- mentioning your center frequency, jitter
>requirements, and power consumption needs will get you more response.
>Spin it not as "why won't my FPGA work" but as "what approach should I
>take", possibly mentioning what you've just learned about the FPGA
approach.
>
>There's some smart folks over there, and many of the ones who can help
>you don't frequent this group.


Thanks for the advice, I posted a topic on sci.electronics.design to see
their take on it.

>> Could we potentially expect better performance with a programmable
logic
>> chip instead of an FPGA?
>
>Field Programmable Gate Array -- what's not programmable logic about
>that? You mean PAL?

Sorry, yes, I forgot the acronym for a while. Essentially I was asking if
we would have better luck with a different programmable logic system. Maybe
not going so far as making our own silicon (since this is essentially one
off design for a specific research problem),but...

>I suspect that the route to take doing this in digital logic is to
>isolate the logic that's actually doing the digital processing of the
>clock, and do _just_ that action with it. If you can control it from an
>FPGA through suitably isolated signals well and good. If the problem
>with the FPGA is all the signals everywhere on the chip coupling into
>each other a little bit, making thresholds noisy, then replacing all
>that with 74AC logic or whatever is fast enough (can you even get ECL
>any more?) and keeping it _quiet_ would probably help.

74AC is an idea, at least to test, but in the end it might be more power
hungry than we would like. This is an avenue for me to explore however.

The next immediate step I'm taking is to use the nice function generator to
clock the fpga, and see if there is any jitter improvement. That alone
could be worth transferring the entire design to another logic system.


>> The clock source is a generic crystal generator. Unfortunately I didn't
>> have the chance to measure the clock jitter and measuring it now
through
>> the fpga results in some crazy readings (~1hz at 50 Mhz, or 100 times
worse
>> than our pll output jitter)
>
>Every high-precision problem that I've ever worked on has been like
>peeling an onion. Any time you're trying to measure or control things
>in the parts-per-million your effort becomes a lot like peeling an onion
>-- you tear a layer off, you cry a lot, and you find that the problem is
>a little smaller. Then you recover your composure and you do it again.
>
>Don't expect this to be any different...
>
>--
>Tim Wescott
>Control system and signal processing consulting
>www.wescottdesign.com


Thanks for all your help.



From: steveu on 15 Jun 2010 04:56
>Vladimir Vassilevsky <nospam(a)nowhere.com> wrote:
>(snip)
>
>> Thanks for the link. Interesting reading; although in the real world
>> they rarely give out *any* jitter specs for digital parts. Yes, jitter
>> is crucial in Class D; and this is one of the reasons why naive digital

>> amplifiers have mediocre performance. Other area where it matters is the

>> RF signal generation.
>
>This reminds me of the stories 30 years ago that Class D audio
>amplifiers at higher powers would become popular and affordable
>in a short number of years. Now, 30 years later, I hear even
>less about them. Now that we have much better high-power
>transistors, presumably better for both analog and digital
>designs, why is it that Class D never caught on.
>
>(Especially with the "digital is always better" mindset
>that so many have now.)

Never caught on? What do you think is inside all those slimline home
theatre boxes that can genuinely put out hundreds of watts RMS without
melting?

Class D amps have been normal in TVs for decades. They are used in portable
equipment (e.g. cell phone and MP3 player amps) for their compactness, low
heat, and low battery draw. Class D is a huge business.

Steve

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