Prev: hi
Next: speed grade and temperature grade aren't marked??
From: Philip Pemberton on 24 May 2010 10:17
On Mon, 24 May 2010 01:26:07 +0100, Brian Drummond wrote:

> I don't do Verilog but it makes sense that there's an equivalent to
> setting attributes for such things in VHDL. And applying them directly
> to the correct signals will save warnings elsewhere...

I had another look at the constraints manual last night and found what I
was looking for. Apparently, the syntax I was looking for was:
(* IOB="TRUE" *) output sdram_xyz;

(replace 'output sdram_xyz' with the I/O spec).

This also turned up a nasty INTERNAL_ERROR bug in Xst, see my other
thread for more info on this (my second post in that thread contains an
explanation of the bug, and a workaround).

> Be aware that XST is finicky though. Your "FORCE" attributes may merely
> result in "constraint is being ignored" warnings unless everything else
> lines up right (duplicate regs not being optimised away) so if you don't
> get what you expect in the .mrp, check the synth report carefully...

Actually, it seems that IOB=FORCE makes Xst bail out if it can't honour
the constraint. Some of the SDRAM controller cache logic uses BA
internally; setting IOB=FORCE stops the Translate process from
completing. Use IOB=TRUE, and ISE appears to add a couple of extra FFs to
allow SDRAM_BA to be pushed into the IOB.

I've also noticed that it's running the SDRAM pins in slew-rate limited
(SLOW) mode, so I'm going to see if adding a "SLEW=FAST" constraint in
the UCF helps out any (hopefully it'll get the setup/hold times down from
~6ns to something a little more reasonable).

--
Phil.
usenet10(a)philpem.me.uk
http://www.philpem.me.uk/
If mail bounces, replace "10" with the last two digits of the current year
First  |  Prev  | 
Pages: 1 2 3 4
Prev: hi
Next: speed grade and temperature grade aren't marked??