Digital-to-Analog Converter LTC 2624, Spartan-3A
in [FPGA]
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From: mlajevar on 3 Jan 2010 22:25 Hello I am trying to write a vhdl code for DAC2624 on spartan3E,but I don't know how much I have to consider for SPI_SCK,should it be the same as my main clk which is 50Mhz? I wrote a vhdl code for ADC1407_1 and amplifier6912_1 on partan3E , I considerSPI_SCK to be 1Mhz in there ,but I don't know aboy DAC?should it be same? --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.com
From: mlajevar on 3 Jan 2010 23:01 Hello I am trying to write a vhdl code for DAC2624 on spartan3E,but I don't know how much I have to consider for SPI_SCK,should it be the same as my main clk which is 50Mhz? I wrote a vhdl code for ADC1407_1 and amplifier6912_1 on partan3E , I considerSPI_SCK to be 1Mhz in there ,but I don't know aboy DAC?should it be same? --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.com
From: Frank Buss on 4 Jan 2010 02:07 mlajevar wrote: > I am trying to write a vhdl code for DAC2624 on spartan3E,but I don't know > how much I have to consider for SPI_SCK,should it be the same as my main > clk which is 50Mhz? First see the datasheet of the LTC2624, if such a high clock is allowed. But it doesn't make sense. Even if you want to update all 4 DACs with different values, you'll need 96 bits and the maximum bandwith of the DACs is 180 kHz, so the maximum required clock is 17 MHz. Create a clock which is sufficient for your required output update rate. And it is much easier to implement it with a DAC clock of 50MHz/n, with n>=2. -- Frank Buss, fb(a)frank-buss.de http://www.frank-buss.de, http://www.it4-systems.de
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