Disable SR when more than one pipe is enabled
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From: Jesse Barnes on 27 Jan 2010 12:00 On Wed, 27 Jan 2010 15:19:08 +0530 David John <davidjon(a)xenontk.org> wrote: > Self Refresh should be disabled on dual plane configs. > Otherwise, as the SR watermark is not calculated for > such configs, switching to non VGA mode causes FIFO > underrun and display flicker. > > This fixes Korg Bug # 14897. > > Signed-off-by: David John <davidjon(a)xenontk.org> > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 45da78e..46d7c0c 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -2519,6 +2519,10 @@ static void g4x_update_wm(struct drm_device *dev, int planea_clock, > sr_entries = roundup(sr_entries / cacheline_size, 1); > DRM_DEBUG("self-refresh entries: %d\n", sr_entries); > I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); > + } else { > + /* Turn off self refresh if both pipes are enabled */ > + I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) > + & ~FW_BLC_SELF_EN); > } > > DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n", > @@ -2562,6 +2566,10 @@ static void i965_update_wm(struct drm_device *dev, int planea_clock, > srwm = 1; > srwm &= 0x3f; > I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); > + } else { > + /* Turn off self refresh if both pipes are enabled */ > + I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) > + & ~FW_BLC_SELF_EN); > } > > DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", > @@ -2630,6 +2638,10 @@ static void i9xx_update_wm(struct drm_device *dev, int planea_clock, > if (srwm < 0) > srwm = 1; > I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN | (srwm & 0x3f)); > + } else { > + /* Turn off self refresh if both pipes are enabled */ > + I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) > + & ~FW_BLC_SELF_EN); > } > > DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", > Great! Looks like the docs were a bit misleading here. Disabling self-refresh for dual plane configs is the safest thing to do. Eric, please apply asap. Should probably go to stable as well. Signed-off-by: Jesse Barnes <jbarnes(a)virtuousgeek.org> -- Jesse Barnes, Intel Open Source Technology Center -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo(a)vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
From: David John on 28 Jan 2010 02:00 On 01/27/2010 10:21 PM, Jesse Barnes wrote: > On Wed, 27 Jan 2010 15:19:08 +0530 > David John <davidjon(a)xenontk.org> wrote: > >> Self Refresh should be disabled on dual plane configs. >> Otherwise, as the SR watermark is not calculated for >> such configs, switching to non VGA mode causes FIFO >> underrun and display flicker. >> >> This fixes Korg Bug # 14897. >> >> Signed-off-by: David John <davidjon(a)xenontk.org> >> >> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c >> index 45da78e..46d7c0c 100644 >> --- a/drivers/gpu/drm/i915/intel_display.c >> +++ b/drivers/gpu/drm/i915/intel_display.c >> @@ -2519,6 +2519,10 @@ static void g4x_update_wm(struct drm_device *dev, int planea_clock, >> sr_entries = roundup(sr_entries / cacheline_size, 1); >> DRM_DEBUG("self-refresh entries: %d\n", sr_entries); >> I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); >> + } else { >> + /* Turn off self refresh if both pipes are enabled */ >> + I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) >> + & ~FW_BLC_SELF_EN); >> } >> >> DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n", >> @@ -2562,6 +2566,10 @@ static void i965_update_wm(struct drm_device *dev, int planea_clock, >> srwm = 1; >> srwm &= 0x3f; >> I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); >> + } else { >> + /* Turn off self refresh if both pipes are enabled */ >> + I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) >> + & ~FW_BLC_SELF_EN); >> } >> >> DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", >> @@ -2630,6 +2638,10 @@ static void i9xx_update_wm(struct drm_device *dev, int planea_clock, >> if (srwm < 0) >> srwm = 1; >> I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN | (srwm & 0x3f)); >> + } else { >> + /* Turn off self refresh if both pipes are enabled */ >> + I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) >> + & ~FW_BLC_SELF_EN); >> } >> >> DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", >> > > Great! Looks like the docs were a bit misleading here. Disabling > self-refresh for dual plane configs is the safest thing to do. > > Eric, please apply asap. Should probably go to stable as well. > > Signed-off-by: Jesse Barnes <jbarnes(a)virtuousgeek.org> > [ Adding Eric and stable (for 2.6.32 series) to CC] Regards, David. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo(a)vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
From: Eric Anholt on 4 Feb 2010 11:40
On Wed, 27 Jan 2010 15:19:08 +0530, David John <davidjon(a)xenontk.org> wrote: > Self Refresh should be disabled on dual plane configs. > Otherwise, as the SR watermark is not calculated for > such configs, switching to non VGA mode causes FIFO > underrun and display flicker. > > This fixes Korg Bug # 14897. Applied. Thanks! |